• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• v.14 no.2
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• Journal of Power Electronics
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• v.11 no.6
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• pp.811-818
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• 2011

Modulation strategies for multilevel inverters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of dc voltage sources. This makes the average power drawn from different dc voltage sources unequal and time varying. Therefore, the dc voltage sources are unregulated and require that corrective control action be incorporated. In this paper, first two new selections are proposed for determining the dc voltage sources values for asymmetric cascaded multilevel inverters. Then two modulation strategies are proposed for the dc power balancing of these types of multilevel inverters. Using the charge balance control methods, the power drawn from all of the dc sources are balanced except for the dc source used in the first H-bridge. The proposed control methods are validated by simulation and experimental results on a single-phase 21-level inverter.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1162-1170
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• 2019

Finite-control-set model predictive control (FCS-MPC) is a promising control scheme for two-level voltage-source inverters (TL-VSIs). However, two main issues arise in the classical FCS-MPC method: an exponentially-increasing computational time and a low steady-state performance. To solve these two issues, a novel FCS-MPC method has been proposed for n-phase TL-VSIs in this paper. The basic idea of the proposed method is to carry out the FCS-MPC scheme of TL-VSIs for one leg by one leg, like a "pipeline". Based on this idea, the calculations are reduced from exponential time to linear time and its current waveforms are improved by applying more switching states per sampling period. The cases of three-phase and five-phase TL-VSIs were tested to verify the effectiveness of proposed method.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.2
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• pp.53-57
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• 2012

The mathematical model of a three-phase voltage source pulse-width modulation (PWM) DC/AC inverter is non-linear, and in view of the traditional linear control strategy it can not meet the requirements of designing a high-performance inverter. What's more, when the loads are not pure resistive loads, the inverter further requires that the controller possess high-performance. This paper proposes a nonlinear control strategy for the inverter called Passivity-based Control. We can alter the inverter model in three-phase abc coordinate to two-phase synchronous rotating dq coordinate for establishing the port-control Hamiltonian (PCH) model for this system. We can control the distribution of energy in the system to achieve the control aim. Simulation results show that the passivity-based control method can make this system possess a level of high-performance that is both robust and dynamic.

• Journal of Power Electronics
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• v.17 no.1
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• pp.67-75
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• 2017

Due to the excessive zero-sequence voltage in dual three-level inverter fed open-end winding induction motor systems, zero-sequence circumfluence which is harmful to switching devices and insulation is then formed when operating in a single DC voltage source supplying mode. Traditionally, it is the mean value instead of instantaneous value of the zero-sequence voltage that is eliminated, through adjusting the durations of the operating vectors. A new strategy is proposed for zero-sequence voltage elimination, which utilizes unified voltage modulation and a decoupled SVPWM strategy to achieve two same-sized equivalent vectors for an angle of $120^{\circ}$, generated by two inverters independently. Both simulation and experimental results have verified its efficiency in the instantaneous value elimination of zero-sequence voltage.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1480-1489
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• 2017

In this study, a carrier-based pulse-width modulation (PWM) method for two-level voltage source inverters in the over-modulation region is proposed. Based on the superposition principle, the reference voltage vectors outside the linear modulation boundary are adjusted to relocate to the vector hexagon, while their fundamental magnitudes are retained. In accordance with the adjusted reference vector, the corresponding modulated waves are respectively deduced in over-modulation mode I and II to generate the gate signals of the power switches, guaranteeing the linearity of the fundamental output phase voltage in the over-modulation region. Moreover, due to the linear relationship between the voltage vector and the duty ratios, the complicated sector identification and holding angle calculation found in previous methods are avoided in the modulated wave synthesis, which provides great simplicity for the proposed carrier-based over-modulation strategy. Experimental results demonstrate the effectiveness and validity of the proposed method.

• Journal of Power Electronics
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• v.18 no.1
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• pp.116-128
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• 2018

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.120-126
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• 2021

DC-link capacitors are one of the main components in two-level three-phase voltage source inverters (VSIs); they provide the pulsating input current and stabilize the vacillating DC-link voltage. Ideally, the larger the capacitance of DC-link capacitors, the better the DC-link voltage stabilizes. However, high capacitance increases the cost and decreases the power density of VSI systems. Therefore, the capacitance should be chosen carefully on the basis of the DC-link voltage ripple requirement. However, the DC-link voltage ripple is dependent on the pulse-width modulation (PWM) strategy. This study especially presents a DC-link voltage ripple analysis when the minimum loss discontinuous PWM strategy is applied. Furthermore, an equation for the selection of the minimum capacitance of DC-link capacitors is proposed. Experimental results with R-L loads are also provided to verify the effectiveness of the presented analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.126-133
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• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.