• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.243-250
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• 2009

This paper provides an novel two-stage LED driver circuit for LED lighting equipment. The proposed driver circuit reduces voltage stress in LED driver circuit by using multi-level output voltage of PFC flyback converter. The proposed circuit satisfies IEC61000-3-2 class C regulation that is applied to lighting equipment over 25W and uses PWM to control brightness of wide extent. In this paper, the principle of proposed driver circuit is presented. A prototype has been built and tested. The experimental results are presented to show the validity of the proposed circuit.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1272-1280
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• 2014

This paper presents solutions for fault detection and diagnosis of two-level, three phase voltage-source inverter (VSI) topologies with IGBT devices. The proposed solutions combine redundant standby VSI structures and contactors (or relays) to improve the fault-tolerant capabilities of power electronics in applications with safety requirements. The suitable combination of these elements gives the inverter the ability to maintain energy processing in the occurrence of several failure modes, including short-circuit in IGBT devices, thus extending its reliability and availability. A survey of previously developed fault-tolerant VSI structures and several aspects of failure modes, detection and isolation mechanisms within VSI is first discussed. Hardware solutions for the protection of power semiconductors with fault detection and diagnosis mechanisms are then proposed to provide conditions to isolate and replace damaged power devices (or branches) in real time. Experimental results from a prototype are included to validate the proposed solutions.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.246-247
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• 2013

This paper investigates control algorithms for a doubly fed induction generator with a back-to-back three-level neutral-point clamped voltage source converter in medium voltage wind power system under unbalanced grid conditions. Control algorithms to compensate for unbalanced conditions have been investigated with respect to four performance factors; fault ride-through capability, instantaneous active power pulsation, harmonic distortions, and torque pulsation. The control algorithm having zero amplitude of torque ripple shows the most cost-effective performance concerning torque pulsation. The least active power pulsation is produced by control algorithm that nullifies the oscillating component of the instantaneous stator active and reactive power. Combination of these two control algorithms depending on the operating requirements and depth of grid unbalance presents most optimized performance factors under the generalized unbalanced operating conditions leading to high performance DFIG wind turbine system. The proposed control algorithms are verified through transient response in the simulation.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.273-274
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• 2012

This paper investigates control algorithms for a doubly fed induction generator(DFIG) with a back-to-back three-level neutral-point clamped voltage source converter in medium voltage wind power system under unbalanced grid conditions. Two different control algorithms to compensate for unbalanced conditions are proposed. Evaluation factors of control algorithm are fault ride-through(FRT) capability, efficiency, harmonic distortions and torque pulsation. Zero regulated negative sequence stator current control algorithm has the most effective performance concerning FRT capability and efficiency. Ripple-free control algorithm nullifies oscillation component of active power and reactive power. Ripple-free control algorithm shows the least harmonic distortions and torque pulsation. Combination of zero regulated negative sequence stator current and ripple-free control algorithm control algorithm depending on the operating requirements and depth of grid unbalance presents the most optimized performance factors under the generalized unbalanced operating conditions leading to high performance DFIG wind turbine system.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1706-1715
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• 2016

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2008.03a
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• pp.589-596
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• 2008

Performance of a pulsed heat source high temperature inert gas plasma MHD electrical power generator, which can be one of the candidates of space-based laser-to-electrical power converter, is examined by a time dependent two dimensional numerical simulation. In the present MHD generator, the inert gas is assumed to be ideally heated to about $10^4K$ pulsed-likely within short time(${\sim}1{\mu}s$) in a stagnant energy input volume, and the energy of high temperature inert gas is converted to the electricity with the medium of pure inert gas plasma without seeding. The numerical simulation results show that an enthalpy extraction ratio(=electrical output energy/pulsed heat energy) of several tens of % can be achieved, which is the same level as the conventional seeded non-equilibrium plasma MHD generator. Although there still exist many phenomena to be clarified and many problems to be overcome in order to realize the system, the pulsed heat source high temperature inert gas MHD generator is surely worth examining in more detail.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.151-155
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• 2016

In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter's output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.462-468
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• 2012

In this paper, an adaptive digital automatic gain control(AGC) algorithm with two stages is proposed. AGC technique is crucial for mobile communication equipment because path loss in wireless channel and gain fluctuation in receiver front-end continuously change the received signal strength. Furthermore, adaptive criteria should be applied to the design of AGC algorithm in order to support many waveforms with one SDR communication device. With these reasons, a two-stage structure is proposed to satisfy both flexibility and adaptiveness. Compared with conventional method, it also requires shorter convergence time. Numerical results show that the gain value of variable gain amplifier(VGA) is converged within proper time and proposed scheme controls the input level of analog to digital converter(ADC) to be stable during long range of time.