• KIEE International Transactions on Electrophysics and Applications
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• 제11C권4호
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• pp.113-119
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• 2001

This paper presents a model for a pin-to-cylinder discharge type ozonizer, which utilizes the superposition of surface discharge and corona discharge operation. By changing the gas flow rate, the discharge power and the number of SDO units, the characteristics of ozone concentration ( $O_{3con}$), ozone generation ( $O_{3g}$) and ozone yield ( $O_{3Y}$) were investigated. Using one SDO unit the maximum values of $O_{3con}$, $O_{3g}$ and $O_{3Y}$ were found as 8100[ppm], 1623[mg/h] and 213[g/kWh] respectively. With two SDO units the corresponding values were found as 12800[ppm], 2893[mg/h] and 248[g/kWh] respectively. Hence using two SDO units the efficiency was improved by 16[%].y 16[%].

• 한국통신학회논문지
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• 제21권1호
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1125-1128
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• 1998

A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.255-258
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• 1996

A new low conduction loss, low cost zero-voltage-transition power factor correction circuit(PFC) is presented. Conventional PFC which consists of a bridge diode and a boost converter(one switch) always has three semiconductor conduction drops. Two switch type PFCs reduces conduction loss by reducing one conduction drop but the cost is increased because of increased number of active switches. The proposed PFC reduces conduction loss with one switch, which allows low cost. Conduction loss improvement is a little bit less than that of two switch type, but very close up. Operation and features are comparatively illustrated and verified by simulation and experimental results of 1 kW laboratory prototype.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.293-299
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• 2016

Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

• 한국정보과학회논문지:소프트웨어및응용
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• 제31권1호
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• pp.89-99
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• 2004

본 논문에서는 코드 변환 과정과 축약, 탈락, 불규칙 활용 둥으로 변형된 형태소의 원형을 복원하고 분석 후보를 생성하는 등의 과정을 거치지 않고 형태소 사전에서 제공되는 인접 조건에 대한 검사만으로 형태소 분석을 하는 방법을 제안한다. 인접 조건 검사는 복잡한 연산을 하지 않고 단순한 비트 연산만으로 할 수 있기 때문에 제안된 방법은 초고속 형태소 분석기 구현에 적합하다. 본 논문에서 제안한 방법에 따라 구현된 한국어 형태소 분석기 MACH는 1.13 GHz Pentium III 개인용 컴퓨터에서 대략 5분/GB의 분석 속도를 보였으며, 분석 정확도는 99.2 %로 기존의 다른 분석기와 큰 차이가 없었다.

• Journal of Advanced Marine Engineering and Technology
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• 제15권1호
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• pp.85-95
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• 1991

All physical systems are nonlinear to some degree. The examples are relay, backlash, deadzone, saturation element and so on. In the linear control system design, it is useful method to restrict the nonlinearity to the linearity of system over the operation range. It is worth noting that nonlinearities may be intentionally introduced in to a system. A simple of an intentional non-linearity is the Bang-Bang controller which uses the On-Off relay. In this paper, an angular position servosystem made of a DC servomotor controlled by a microcomputer is discribed. Authors use two methods in the design of controller. The one is linear controller designed by the optimal feedback control theory only and the other is nonlinear controller designed by On-Off relay with optimal feedback control theory. To do the real time control, the controller is designed by using 16bit personal computer and A/D.D/A converter(12bit) is used in order to convert the signal. According to this way, the results from real time control are as follows. 2) Under the On-Off controller with hysterisis the influence of disturbance is considerably smaller than the linerar controller. 3) An increase in the sampling period has a destabilizing effect. 4)In the controller performance, the response time of the On-Off controller is longer than that of the linear controller. To close, we note that the On-Off controller with hysterisis is more attractive than the linear controller in the presence of the input limit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.443-450
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• 2013

This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.

• 한국통신학회논문지
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• 제33권1C호
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• pp.68-78
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• 2008

The transmission of multimedia information over error-prone channels such as wireless networks has become an important area of research. In this paper, we propose two Error Concealment(EC) schemes for wireless transmission of JPEG2000 image. The Multiple Representation(MR) is employed as the preprocessing in our schemes, whereas the main error concealing operation is applied in wavelet domain at receiver side. The compressed code-stream of several subsampled versions of original image is transmitted over a single channel with random bit errors. In the decoder side, the correctly reconstructed wavelet coefficients are utilized to recover the corrupted coefficients in other sub-images. The recovery is carried out by proposed basic(MREC-BS) or enhanced(MREC-ES) methods, both of which can be simply implemented. Moreover, there is no iterative processing during error concealing, which results a big time saving. Also, the simulation results confirm the effectiveness and efficiency of our proposed schemes.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.