• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of KSNVE
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• v.6 no.2
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• pp.163-177
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• 1996

An investigation on thermohydraulic stability of flow oscillations in the CANada Deuterium Uranium-600(CANDU-6) heat transport system has been conducted. Flow oscillations in reactor coolant loops, comprising two heat sources and two heat sinks in series, are possibly caused by the response of the pressure to extraction of fluid in two-phase region. This response consists of two contributions, one arising from mass and another from enthalpy change in the two-phase region. The system computer code used in the investigation os SOPHT, which is capable of simulating steady states as well as transients with varying boundary conditions. The model was derived by linearizing and solving one-dimensional, homogeneous single- and two-phase flow conservation equations. The mass, energy and momentum equations with boundary conditions are set up throughout the system in matrix form based on a node-link structure. Loop stability was studied under full power conditions with interconnecting the two compressible two phase regions in the figure-of-eight circuit. The dominant function of the interconnecting pipe is the transfer of mass between the two-phase regions. Parametric survey of loop stability characteristics, i. e., damping ratio and period, has been made as a function of geometrical parameters of the interconnection line such as diameter, length, height and orifice flow coefficient. The stability characteristics with interconnection line has been clarified to provide a simple criterion to be used as a guide in scaling of the pipe.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.25-27
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• 2010

This paper presents a gain and phase mismatch calibration technique for an image-reject RF receiver. The gain mismatch is calibrated by directly measuring the output signal amplitudes of two signal paths. The phase mismatch is calibrated by measuring the output amplitude of the final IF output at the image band. The calibration of the gain and phase mismatch is performed at power-up, and the normal operation of the RF receiver does not interfere with the mismatch calibration circuit. To verify the proposed technique, a 2.4-GHz Weaver image-reject receiver with the gain and phase mismatch calibration circuit is implemented in a 0.18-${\mu}m$ CMOS technology. The overall receiver achieves a voltage gain of 45 dB and a noise figure of 4.8 dB. The image rejection ratio(IRR) is improved from 31 dB to 59.76 dB even with 1 dB and $5^{\circ}$ mismatch in gain and phase, respectively.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1347-1356
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• 2018

In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from $-{\pi}$ to ${\pi}$. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.