• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.34-42
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• 2012

Low density parity check (LDPC) code is widely used, since it shows superior performance close to Shannon limit and its decoding complexity is lower than turbo code. Recently, it is used as a channel code to decode Wyner-Ziv frames in distributed video coding (DVC) system. In this paper, we propose an efficient method to design the parity check matrix H of LDPC codes. In order to apply LDPC code to DVC system, the LDPC code should have rate compatibility. Thus, we also propose a method to merge check nodes of LDPC code to attain the rate compatibility. LDPC code is designed using ACE algorithm and check nodes are merged for a given code rate to maximize the error correction capability. The performance of the designed LDPC code is analyzed extensively by computer simulations.

• ETRI Journal
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• v.30 no.1
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.4
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• pp.11-16
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• 2004

A simple stopping criterion for iterative decoding based on min-sum processing is presented. While most stopping criteria suggested in the literature, are based on Cross Entropy (CE) and its simplification, the proposed stopping criterion is to check if a decoded sequence is a valid codeword along the encoder trellis structure. This new stopping criterion requires less computational complexity and saves mem4)ry compared to the conventional stopping rules. The numerical results are presented on the 3GPP turbo code and a Serially Concatenated Convolutional Cods (SCCC).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.553-556
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• 2005

It is analyzed that WAP packet transmission time to improve performance of WAP using SAR algorithm in Bluetooth channel. The order for SAR algorithm to improve the transfer capability, it is fragmented in WTP total messages that are coming down from upper layer and then the packets are sent one at time in baseband. And it is studied that transmission time for WAP over bluetooth according to DM1, DM3 or DM5 packet type using SAR algorithm in Bluetooth piconet environment. This SAR algorithm decreases WAP packet transmission time of L2CAP baseband packets by sending packet which are spanning multiple slots.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.281-282
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• 2008

Turbo equalizers which use MAP (maximum a posteriori probability) equalizer or MMSE (minimum mean square error) equalizer have shown high performance and adoptability [1], [2]. In this paper, we show that the BP (belief propagation) algorithm can also be applied in equalizer and when it is connected with channel code, it can replace the MAP equalizer with similar complexity and performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.149-157
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• 2006

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication system. As the number of iterations increases, it can achieves remarkable BER performance over AWGN channel environment. However, if the number of iterations is increased in the several channel environments, any further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. To solve this problems, it is necessary to device an efficient criterion to stop the iteration process and prevent unnecessary delay and computation. In this paper, it proposes an efficient and simple criterion for stopping the iteration process in turbo decoding. By using variance values of LLR in turbo decoder, the proposed algerian can largely reduce the average number of iterations without BER performance degradation in all SNR regions. As a result of simulation, the average number of iterations in the upper SNR region is reduced by about $34.66%{\sim}41.33%$ compared to method using variance values of extrinsic information. the average number of iterations in the lower SNR region is reduced by about $13.93%{\sim}14.45%$ compared to CE algorithm and about $13.23%{\sim}14.26%$ compared to SDR algorithm.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.105-114
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• 2000

In this paper, we propose a bandwidth-efficient channel coding scheme using the turbo trellis-coded modulation with multiple symbol detection. The turbo code can achieve good bit error rates (BER) at low SNR. That comprises two binary component codes and an interleaver. TCM codes combine modulation and coding by optimizing the euclidean distance between codewords. This can be decoded with the Viterbi or the symbol-by- symbol MAP algorithm. But we present the MAP algorithm with branch metrics of the Euclidean distance of the first phase difference as well as the Lth phase difference. The study shows that the turbo trellis-coded modulation with multiple symbol detection can improve the BER performance at the same SNR.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.257-265
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• 2000

Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics in each decoding step, and uses the information to the next decoding step. Viterbi decoder, which is for a convolutional code, runs continuous mode, while Turbo Code decoder runs by block unit. There are algorithms used in a decoder : which are MAP(maximum a posteriori) algorithm requiring very complicated calculation and SOVA(soft output Viterbi algorithm) using Viterbi algorithm suggested by Hagenauer, and it is known that the decoding performance of MAP is better. The result of this make experimentation shows that the performance of SOVA, which has half complex algorithm compare to MAP, is almost same as the performance of MAP when the SOVA decoding performance is supplemented with Robust equalization techniques.

• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.