• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.215-215
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• 2010

The feasibility of InSbTe (IST) chalcogenide materials prepared by metalorganic chemical vapor deposition (MOCVD) for phase-change memory (PRAM) applications was demonstrated. Films grown below $225^{\circ}C$ exhibited an amorphous structure, and the films grown at $300^{\circ}C$ Cincluded various crystalline phases such as In-Sb-Te, In-Sb, In-Te, and Sb-Te. The composition of the amorphous films grown at $225^{\circ}C$ was dependent on the working pressure. Films grown at $225^{\circ}C$ exhibited a smooth morphology with a root mean square(rms) roughness of less than 1nm, and the step-coverage of the films grown on a trench structure with an aspect ratio of 5:1 was greater than 90%. An increase in deposition time increased the filling rate, while retaining the conformal step-coverage. Films grown at $225^{\circ}C$ for 3h in a working pressure of $13{\times}10^2$ Pa exhibited a reproducible and complete filling in a trench structure.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.546-550
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• 2004

Two fabrication approaches are proposed to planarize the sacrificial layer over hollow structures. One is the photoresist filling method that makes use of photolithography, thermal curing and plasma ashing. The other is the lamination method that is applying pressure and temperature to the organic film over the hollow structures. The fabrication results are compared with those of CMP process. Trenches and cavities with various dimensions have been made for the porposed process. Upon measuring the planarization levels, they are dependent on planarization methods and the geometrical size of hollow structures. The photoresist filling method is so strongly dependent on the width and depth of trenches that we have problems to use it for large dimensional trenches. To the contrary, the flatness of sacrificial layer over the trenches was found to be almost independent of trench dimensions for the lamination method. A CMP process shows the most excellent results, but the fabrication is complicated and the access to it is not so easy. It is important to choose the proper planarization method by considering the required flatness levels, materials to be planarized, and connection between the planarization step and the previous or the following process of it.

• Korean Journal of Materials Research
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• v.9 no.2
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• Proceedings of the Korean Geotechical Society Conference
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• 1999.03a
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• pp.513-520
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• 1999

20 million tons of coal ash has been produced in Korea annually. This causes the environmental problems and the cost of land for ash pond. However the amount of coal ash for recycling is small because of the low level of recycling technology and the ignorance. As the coal ash has the significant engineering properties, it can be utilized as soft ground stabilizer, backfill materials and so forth. The purpose of this paper is to summarize some of the recycling methods of coal ash. One is structural backfill materials, the other is flowable fill. Optimal mixture ratio(fly ash : bottom ash) is determined for structural backfill materials and the model test is performed. The model test accompanied with physical tests were executed for identifying that the flowable fly ash can be used as fill materials such as trench back filling.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Journal of Surface Science and Engineering
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• v.38 no.1
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• pp.28-36
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• 2005

In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16～0.24 11m with aspect ratio of 4.17～6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

• International Journal of Railway
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• v.7 no.1
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• pp.16-23
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• 2014

Reduction in railway-induced vibrations in urban areas is a very challenging task in railway transportation. Many mitigation measures can be considered and applied. Among these, a little attention has been paid to trenches. In this study, a numerical investigation on the effectiveness of in-filled trenches with pipes in reducing railway vibrations due to passing trains is presented. Particularly, a series of two-dimensional dynamic analysis was performed to model the behavior of ballasted railway track under harmonic load with ABAQUS software as a Finite Element method. In so doing, two types of in-filled trenches with pipes with steel and concrete materials have been investigated in this paper. In addition, effectiveness of pipes made of steel and concrete, filled with loose sand and clay in railway-induced vibration reduction has been assessed. The results point out that using in-filled trench with pipes does not effective a lot on railway-induced vibration reduction in comparison to other railway-induced vibration reduction methods. However, in-filled trenches with steel pipes are much more effective than in-filled trenches with concrete pipes. Moreover, filling pipes with loose sand and clay does not have any effect on vibration reduction efficiency of these in-filled trenches.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.11 no.1
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• pp.145-151
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• 1991

The final purpose of this study is to examine the uses of coal ash, by-product from thermal power plant as a type of filling-embankment materials and the reuses of ash ponds. In this time, to investigate the dynamic properties, we made the test piece specimen with coal ashes, and obtained the damping ratio. In place(ash pond), the damping property by underground wall was investigated before and after soil improvements. The damping ratio of coal ash test piece specimen of 12% cement is the highest and that of 9% cement or chemical grout, that of 6% cement is in order. In same coal ash test piece, the damping ratio increases with decreasing the void ratio. In conclusion, it could be said that the damping ratio increases with the stiffness of materials. In the ash pond, the damping effect is the most when trench is set through the vibration wave propagation course, and when soil is improved the higher stiffness of the improved soil is, the more damping effect appeared. It is justified to obtain not only the dropping of permeability and the strength increase, but also the damping effect fairly by soil improvements.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.