• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.929-935
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• 2005

This paper contains a review of methods to analise static and dynamic properties of trap states in TFTs. The Gap Density of States is extracted from C-V and I-V characteristics. Switch on transients and small signal ac measurements are used in conjunction with simulation and an analytic model to extract traps dynamic parameters.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1435-1438
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• 1994

The effects of Ge composition variation in $a-Si_{1-x}Ge_x:H$ alloy p-i-n solar cells on the physical properties and current density-voltage characteristics are analyzed by a new simulation modelling based on the update published experimental datas. The simulation modelling includes newly formulated density of gap density spectrum corresponding to Ge composition variation and utilizes the newly derived generation rate formulars which include the reflection coefficients and can apply to multijunction structures as well as single junction structure. The effects in $a-Si_{1-x}Ge_x:H$ single junction are analyzed through the efficiency, fill factor, open circuit voltage, short circuit current density, free carriers, trap carriers, electric field, generation rate and recombination rate. Based on the results analyzed in single junction structure, the applications to multiple junction structures are discussed and the optimal conditions reaching to a high performance are investigated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.44-51
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• 1999

The electrical conduction mechanism of high dielectric $(Ba,Sr)TiO_3$ (BST) thin film capacitor, which is the promising cell capacitor for high density DRAM, was investigated in low field region (<0.2MV/cm). It is known that the current in the low field region consists of dielectric relaxation current and leakage current. The current-time (I-t) measurement technique under the constant voltage was used for extracting successfully each current component. The conduction mechanism of the BST capacitor was deduced from the dependency of the current on the measurement temperature, strength of electric field, the polarity of applied electric field and post annealing process. From these results, it was suggested that the dielectric relaxation current and the leakage current are originated from the redistribution of internally trapped electron by hopping process and Pool-Frenkel conduction mechanism, respectively. It was also concluded that traps causing these two current components are due to oxygen vacancies within the BST film.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.203-207
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• 2018

In this work, we investigate the effects of lithium doping on the electric performance of solution-processed n-type zinc tin oxide (ZTO)/p-type silicon carbide (SiC) heterojunction diode structures. The proper amount of lithium doping not only affects the carrier concentration and interface quality but also influences the temperature sensitivity of the series resistance and activation energy. We confirmed that the device characteristics vary with lithium doping at concentrations of 0, 10, and 20 wt%. In particular, the highest rectification ratio of $1.89{\times}107$ and the lowest trap density of $4.829{\times}1,022cm^{-2}$ were observed at 20 wt% of lithium doping. Devices at this doping level showed the best characteristics. As the temperature was increased, the series resistance value decreased. Additionally, the activation energy was observed to change with respect to the component acting on the trap. We have demonstrated that lithium doping is an effective way to obtain a higher performance ZTO-based diode.

• Journal of Electrical Engineering and Technology
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• v.12 no.1
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• pp.302-309
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• 2017

The ageing of XLPE cable insulation will lead to the accelerating accumulation of space charge, which will greatly affect the safe operation of the HVDC cable. In order to investigate the influence of different ageing modes on the space charge distribution of the HVDC cable, thermal stressed, electrical stressed and electro-thermal stressed endurance tests were carried out on the XLPE peelings. The tested XLPE peelings were obtained from 160kV HVDC cable insulation. The endurance tests were carried at thermal stress of 363K, electrical stress of 20kV/mm DC and a combination of both. The Pulsed Electro-Acoustic (PEA) method was used to measure the space charge distribution of the samples. The influences of ageing on the trap energy distribution were analyzed based on the isothermal relaxation theory and the decay characteristics of the space charge. The results showed that thermal ageing would help to improve the crystalline morphologies of the XLPE at the early stage. The total amount of space charge decreased compared to the ones before thermal ageing. The long term of electrical stress would result in the cleavage of polymer molecule chains which would intensify the accumulation of space charge and increase the density and depth of electron traps. With a combination of electrical and thermal stress, the injection and migration of space charge were more significant. Besides, the depth and density of electron traps increased rapidly with the increase of endurance time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.547-550
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• 2014

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/$SiO_2$ structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage ($V_{FB}$) shift was positive. Near-interface trap charge density ($N_{it}$) and negative oxide trap charge density ($N_{ox}$) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.859-863
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• 2007

Aluminum oxide films were deposited on n-type 6H-SiC(0001) substrates by RF magnetron sputtering technique for MIS devices applications. Well-behaved C-V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $4.6{\times}10^{10}/cm^2\;eV$ in the upper half of the bandgap. The gate leakage current densities of the MIS structures were about $10^{-8}A/cm^2$ and about $10^{-6}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for a ${\pm}1\;MV/cm$, respectively These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.977-982
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• 2005

Al/AlN/n-type 6H-SiC (0001) MIS structures were prepared by AlN layers on vicinal 6H-SiC(0001) substrates with reactive RF magnetron sputtering method. The AlN films were annealed at $900^{\circ}C$, $N_2$ atmosphere lot 1 minutes showed the best result. With XRD analysis, AlN(0002) peak was clearly found. The typical dielectric constant value of the AlN film in the MIS capacitors was obtained as 8.4 from photo C-V. Also, the gate leakage current density of the MlS capacitor was $10^{-10}\;A/cm^2$ order within the electric field of 1.8 MV/cm. Finally, the amount of interface trap densities, $D_{it}$, was evaluated as $5.3\times10^{10}\;eV^{-1}cm^{-2}$ at (Ec-0.85) eV.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.329-334
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• 2008

Aluminum oxide films were deposited on n-type GaN substrates by RF magnetron sputtering technique for MIS devices applications using optimized conditions, Well-behaved C - V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $9\times10^{10}/cm^2$ eV in the upper bandgap. The gate leakage current densities of the MIS structures were about $10^{-9}A/cm^2$ and about $10^{-4}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for $a{\pm}1MV/cm$, respectively. These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• Journal of Sensor Science and Technology
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• v.5 no.6
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• pp.60-67
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• 1996

The interfacial electrical properties of InSb MIS structure with low temperature remote PECVD $SiO_{2}$ have been characterized. The interlace-state density at mid-bandgap of the MIS structure was about $1{\sim}2{\times}10^{11}\;cm^{-2}eV^{-1}$, when the $SiO_{2}$ film was deposited at $105^{\circ}C$. However, large amount of interlace states and trap states were observed in the MIS structure fabricated at temperatures above $105^{\circ}C$. The time constant of $10^{-4}{\sim}10^{-5}\;sec$ of interface states was extracted from G- V measurement. As the deposition temperature increased, the hysteresis of C- V curves were increased due to the high trap density.