• 대한전기학회논문지
• /
• 제43권4호
• /
• pp.601-606
• /
• 1994

This paper describes the effect of elongation on electrical properties and molecular structrue of high density polyethylene. Thin polyethylene films films obtained dy roll elongation after extruded at 220$^{\circ}C$ and elongated to draw rations of 16. Crystallinity of polyethylene films was measured by X-Ray diffraction and electrical properties were estimated by conductivity and TSC(Thermal Simulated Current). It was foung that the crystallinity increases and the electrical conductivity decreases as the elongation increases. The elongation dependence of electrical conductivity may be explained by the trap density. Thus, the control of polymer structure and crystallinity makes its properties better and can be applicated in order to get more active properties.

• 한국해양공학회지
• /
• 제17권5호
• /
• pp.32-38
• /
• 2003

This study investigates the distribution characteristics and relationship of water quality, and analyzes the spatial and temporal variation and distribution of the pollutant loads at Yeong-il Bay. The results of these analysis, the concentrations of nutrient loads (T-N and T-P), both appeared to be at the maximum value in November, while most small values were taken in May for the T-N, and in August for the T-P. For COD, the maximum concentration was in August, which has much precipitation during the same season, T-N was at the mean, and T-P was at the minimum value. Using the cluster analysis to develop the division of the sea basin by the dendrogram, before and after construction of Pohang New-port, the variation characteristics of water quality of Yeong-il Bay were discussed. The in flowing pollutant loads were transported to the landward by the high-density salinity water volume of the bottom layer therefore, it formed nutrient trap or coastal trapping areas of the pollutant load. By this mechanism, it is clear that the water volume with high-density nutrient exists on both sides of the Pohang New-port. Thus, the sea basins increasing concentration of the pollutant load at Yeong-il Bay are most prevalent at Hyeong-san estuary, the Pohang Old, and New-port. To improve water quality of this sea basin, the reduction of these nutrients loads should be the highest priority.

• 한국결정성장학회지
• /
• 제24권1호
• /
• pp.41-45
• /
• 2014

다양한 공정 조건으로 $SiN_x$와 $SiO_2$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. Plasma enhanced chemical vapor deposition(PECVD)을 이용하여 증착된 $SiN_x$ 박막의 경우, 증착 두께가 증가함에 따라 페시베이션 특성이 향상되는 것을 관찰하였다. 이는 PECVD 증착 공정 중 유입되는 수소 원자들이 실리콘 표면에 존재하는 Dangling bond와 결합하여 소수 캐리어의 재결합 현상을 효과적으로 감소시켰기 때문이다. 건식 산화법으로 형성된 $SiO_2$ 박막은 습식 산화법으로 형성된 것 보다 치밀한 계면 구조를 가짐으로 인하여 약 20배 이상 우수한 패시베이션 특성을 나타내었다. 건식 산화 공정 온도가 증가함에 따라 패시베이션 특성이 열화되는 현상이 발생하였고, Capacitance-voltage(C-V) 및 Conductance-voltage(G-V) 분석을 통하여 $SiO_2$/실리콘 계면에 존재하는 계면 결함 밀도 증가에 의해 나타나는 현상임을 알 수 있었다.

• 한국전기전자재료학회논문지
• /
• 제11권12호
• /
• pp.1122-1127
• /
• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1993년도 하계학술대회 논문집 B
• /
• pp.1268-1270
• /
• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• 한국전기전자재료학회논문지
• /
• 제37권1호
• /
• pp.101-105
• /
• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• 전기전자학회논문지
• /
• 제28권1호
• /
• pp.46-52
• /
• 2024

이번 연구에서 우리는 게이트 산화막을 형성하기 위해 Si을 증착한 후 산화시킨 SiC MOSFET의 전기적 특성을 연구했다. 고품질의 Si/SiO₂ 계면을 제작하기 위해 얇은 Si 층을 SiC epi 층 위에 약 20 nm을 증착한 후 산화하여 게이트 산화막을 약 55 nm로 형성했다. SiC를 산화하여 게이트 산화막을 제작한 소자와 계면 트랩 밀도, 온저항, 전계-효과 이동도의 측면에서 비교했다. 위 소자는 향상된 계면 트랩 밀도 (~8.18 × 10¹¹ eV^-1cm^-2), 전계-효과 이동도 (27.7 cm²/V·s), 온저항 (12.9 mΩ·cm²)을 달성하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.133-133
• /
• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• Bulletin of the Korean Chemical Society
• /
• 제29권10호
• /
• pp.1973-1976
• /
• 2008

Electronic photodepletion spectrum of dibenzo-18-crown-6 with a potassium ion ($K^+$-DB18C6) was obtained in the gas phase using electrospray ionization and quadrupole ion-trap reflectron time-of-flight mass spectrometry. The spectrum exhibited rather a broad absorption band at 36350 $cm^{-1}$, which was tentatively assigned as the origin of the S1 band. The photodepletion spectrum of $Cs^+$-DB18C6 was also obtained to elaborate the effects of metal cations on electronic and geometric structures of metal cation-DB18C6 complexes. We found that the S1 band of $Cs^+$-DB18C6 was red-shifted by 180 $cm^{-1}$ from that of $K^+$-DB18C6. With the results of quantum theoretical calculations using the density functional theory, we suggested that the red-shift arose mainly from weaker binding of $Cs^+$ to DB18C6 than that of K+, which resulted from a larger size of $Cs^+$ than that of the cavity in DB18C6.

• 한국전기전자재료학회논문지
• /
• 제15권10호
• /
• pp.831-837
• /
• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.