• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.583-586
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• 2005

In this paper, millimeter-wave monolithic integrated circuit (MIMIC) low noise amplifier (LNA) for V-band, which is applicable to 58 GHz, we designed and fabricated. We fabricated the module using the fabricated LNA chips. The V-band MIMIC LNA was fabricated using the high performance $0.1\;{\mu}\;m$ ${\Gamma}-gate$ pseudomorphic high electron mobility transistor (PHEMT). The MIMIC LNA was designed using active and passive device library, which is composed $0.1\;{\mu}\;m$ ${\Gamma}-gate$ PHEMT and coplanar waveguide (CPW) technology. The designed V-band MIMIC LNA was fabricated using integrated unit processes of active and passive device. Also we fabricated CPW-to-waveguide fin-line transition of WR-15 type for module. The Transmission Line was fabricated using RT Duroid 5880 substrate. The measured results of V-band MIMIC LNA and Module are shown $S_{21}$ gain of 13.1 dB and 8.3 dB at 58 GHz, respectively. The fabricated LNA chip and Module in this work show a good noise figure of 3.6 dB and 5.6 dB at 58 GHz, respectively.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.391-400
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• 2008

Multi-pulse topology of converters using elementary six-pulse GTO - VSC (gate turn off based voltage source converter) operated under fundamental frequency switching (FFS) control is widely adopted in high power rating static synchronous compensators (STATCOM). Practically, a 48-pulse ($6{\times}8$ pulse) configuration is used with the phase angle control algorithm employing proportional and integral (PI) control methodology. These kinds of controllers, for example the ${\pm}80MVAR$ compensator at Inuyama switching station, KEPCO, Japan, employs two stages of magnetics viz. intermediate transformers (as many as VSCs) and a main coupling transformer to minimize harmonics distortion in the line and to achieve a desired operational efficiency. The magnetic circuit needs altogether nine transformers of which eight are phase shifting transformers (PST) used in the intermediate stage, each rating equal to or more than one eighth of the compensator rating, and the other one is the main coupling transformer having a power rating equal to that of the compensator. In this paper, a two-level 48-pulse ${\pm}100MVAR$ STATCOM is proposed where eight, six-pulse GTO-VSC are employed and magnetics is simplified to single-stage using four transformers of which three are PSTs and the other is a normal transformer. Thus, it reduces the magnetics to half of the value needed in the commercially available compensator. By adopting the simple PI-controllers, the model is simulated in a MATLAB environment by SimPowerSystems toolbox for voltage regulation in the transmission system. The simulation results show that the THD levels in line voltage and current are well below the limiting values specified in the IEEE Std 519-1992 for harmonic control in electrical power systems. The controller performance is observed reasonably well during capacitive and inductive modes of operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.795-805
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• 2012

This paper proposes an algorithm and a hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional system, The pipelined broadcast algorithm is an algorithm which takes advantage of maximum bandwidth of communication bus. But unnecessary synchronization process are repeated, because the pipelined broadcast sends the data divided into many parts. In this paper, the MPI unit for pipeline chain algorithm based on circuit switching removing the redundancy of synchronization process was designed, the proposed architecture was evaluated by modeling it with systemC. Consequently, the performance of the proposed architecture was highly improved for broadcast communication up to 3.3 times that of systems using conventional pipelined broadcast algorithm, it can almost take advantage of the maximum bandwidth of transmission bus. Then, it was implemented with VerilogHDL, synthesized with TSMC 0.18um library and implemented into a chip. The area of synthesis results occupied 4,700 gates(2 input NAND gate) and utilization of total area is 2.4%. The proposed architecture achieves improvement in total performance of MPSoC occupying relatively small area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5B
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• pp.771-776
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• 2010

In this paper, we present an efficient centralized dynamic bandwidth allocation scheme with multicasting for asymmetric 10G-Ethernet Passive Optical Networks (10G-EPONs). The proposed scheme is based on multicast-burst polling and provides quality of service (QoS) with class of service (CoS) to different lasses of packets. It is shown that a well-known conventional interleaved polling scheme severely decreases downstream channel capacity for user traffic when the upstream network load is low (avalanche gate frequency). To overcome this problem, we have proposed a multicast burst polling scheme which shows impressively lower downstream bandwidth consumption compare to IPACT and moreover it did not show the light load penalty problem. Simulation results using an OPNET tool show that the multicast burst polling effectively eliminates light-load penalty and minimizes downstream bandwidth consumption under avalanche gate frequencies.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.11-18
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• 2021

The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.