• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.142-153
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• 2021

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.78-82
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• 2023

Metal oxide semiconductor (MOS) adapting spray-pyrolysis deposition technique has drawn large attention based on their high quality of intrinsic and electrical properties in addition to simple and low-cost processibility. To fully utilize the merits of MOS field-effect transistors (FETs) , transparency, it is important to understand the instability behaviors of FETs under illumination. Here, we studied the photo-induced properties of nc-ZnO/ZnO field-effect transistors (FETs) based on spray-pyrolysis under illumination which incorporating ZnO nanocrystalline nanoparticles into typical ZnO precursor. Our experiments reveal that nc-ZnO in active layer suppressed the light instabilities of FETs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.481-482
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• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.72-72
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• 2012

The next generation electronics need to not only be smaller but also be more flexible. To meet such demands, electronic devices using two dimensional (2D) atomic crystals have been studied intensely. Especially, graphene which have unprecedented performance fulfillments in versatile research fields leads a parade of 2D atomic crystals. In this talk, I will introduce the electrical characterization and applications of graphene for prominently electrical transistors realization. Even the rising 2D atomic crystals such as hexagonal boron nitride (h-BN), molybdenum disulfide (MoS2) and organic thin film for field effect transistor (FET) toward competent enhancement will be mentioned.

• ETRI Journal
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• v.34 no.6
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• pp.966-969
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• 2012

From a practical viewpoint, the topic of electrical stability in oxide thin-film transistors (TFTs) has attracted strong interest from researchers. Positive bias stress and constant current stress tests on indium-gallium-zinc-oxide (IGZO)-TFTs have revealed that an IGZO-TFT with a larger Ga portion has stronger stability, which is closely related with the strong binding of O atoms, as determined from an X-ray photoelectron spectroscopy analysis.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1200-1203
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• 2004

We investigated the molecular aligning capability of a polymer layer containing ceramic nanoparticles which can be used as a gate insulator of organic thin-film transistors (OTFTs). Because of the enhanced dielectric properties arising from the nanoparticles and molecular aligning properties of the polymer, the composite layer provides excellent mobility characteristics of the OTFTs.