• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.146-155
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• 1994

In this paper, we desribe a new system, called BEST, that is used to develop a macromodel or behavioral model easily. It automatically calculates the component values of macromodel represented by equations to satisfy the given specification. Also, it gives the way to analyze both the behavioral model and transistor level circuit, and then compare the analysis results of them to check the correspondence under specific temperature and bias condition, and BEST optimizes the component values of macromodel. Other feature is to characterize MOSFET as switch model which consists of PWL-RC network. Finally, it is possible to generage multi-level netlist which consists of macro/switch/transistor level circuits, and user can determine the trade-off between simulation speed and accuracy. With the graphic user interface form of macromodel development system described above. BEST enable designers to make macromodel by themselves and to uas it. We applied BEST to develop the macromodel for the test circuit and got the 18.6 times simulation speed up with preserving the accuracy within 10% compared to the conventional transistor level circuit simulation. Also, applicability of optimization capability was verified.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1963-1966
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• 2008

We fabricate and evaluate the metal-oxide-semiconductor (MOS) transistor probe with the focused-ionbeam (FIB) for surface electric properties. The probes are designed with the rectangular and V-shaped structures, and their dimensions are determined considering the contact mode operation. The conductive nano tip is grown with FIB system, and deposition condition is controlled for the sharp tip. The fabricated device is applied to the various test patterns like the metal lines and PZT poling regions, and the results show the well defined measurement patterns.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.619-621
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• 2008

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.387.1-387.1
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• 2014

A new class of temperature-sensing materials is demonstrated along with their integration into transparent and flexible field-effect transistor (FET) temperature sensors with high thermal responsivity, stability, and reproducibility. The novelty of this particular type of temperature sensor is the incorporation of an R-GO/P(VDF-TrFE) nanocomposite channel as a sensing layer that is highly responsive to temperature, and is optically transparent and mechanically flexible. Furthermore, the nanocomposite sensing layer is easily coated onto flexible substrates for the fabrication of transparent and flexible FETs using a simple spin-coating method. The transparent and flexible nanocomposite FETs are capable of detecting an extremely small temperature change as small as $0.1^{\circ}C$ and are highly responsive to human body temperature. Temperature responsivity and optical transmittance of transparent nanocomposite FETs were adjustable and tuneable by changing the thickness and R-GO concentration of the nanocomposite.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.312-315
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• 2001

Recently organic electroluminescent devices have been intensively investigated for using in full-color flat-panel display. Since the quantum efficiency of electrophosphorescent device decrease rapidly as the luminance increase, it is desirable to operate the electrophosphorescent display with active matrix rather than passive matrix. Here we report the study of driving electrophosphorescent diode with all organic thin film transistor(OTFT). The structure of electrophosphorescent diode is ITO/TPD/BCP:Ir(ppy)$_3$/BCP/Alq$_3$/Li:Al/Al. In OTFT. polymer is used as an insulator and pentacene as an active layer. Detailed performance of the integrated device will be discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.931-937
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• 2003

The principle of the superconducting vortex flow transistor (SVFT) is based on control of the Abrikosov vortex flowing along a channel. The induced voltage is controlled by a bias current and a control current, instead of external magnetic field. The device is composed of parallel weak links with a nearby current control line. We explained the process to get an I-V characteristic equation and described the method to induce the external and internal magnetic field by the Biot-Savarts law in this paper. The equation can be used to predict the I-V curves for fabricated device. From the equation we demonstrated that the current-voltage characteristics were changed with input parameters. I-V characteristics were simulated to analyze a SVFT with multi-channel by a computer program.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.