• 한국철도학회:학술대회논문집
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• 한국철도학회 2010년도 춘계학술대회 논문집
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• pp.488-497
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• 2010

2001년 KORAIL에 도입된 8100대 신형 전기기관차는 독일 SIEMENS사의 BR152 모델을 국내 설정에 맞도록 들어와 부분 수정 및 보완 통하여, 2003년 8200대 신형 전기기관차를 탄생하도록 한 PROTOTYPE 이다. 8100대 신형전기기관차와 8200대 신형 전기기관차는 유사하지만, 일부 수정되고 개선된 부분 중의 하나가 객차 전원 공급(이하'HEP) 장치이다. 이에 본 논문은 8200대 신형 전기기관차의 HEP 장치에서 무궁화호 객차로 공급되는 HEP 전원의 고조파 왜율에 대하여 원제작사의 조합시험 결과를 바탕으로 현재 운용중인 KORAIL 8200대 신형 전기기관차의 HEP 전원의 고조파 왜율을 실측하여 상호 비교하고, 전원 공급 장치의 고조파 왜율에 대한 국제규격 및 현황을 설명하고자 한다.

• 전력전자학회논문지
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• 제9권4호
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• pp.356-363
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• 2004

본 논문에서는 무정전 전원장치와 같이 일정전압 일정주파수(constant voltage and constant frequency; CVCF) 운전에 사용되는 단상 PWM 인버터의 정밀 전압제어 기법을 다루었으며 정상상태에서 전압 오차를 최소화하기 위해 phase-locked loop(PLL) 기법을 이용한 새로운 전압 제어 방법을 제안하였다. 제안된 제어기법에서는 출력 커패시터 전압과 전류를 이용하여 PLL 보상기를 구성하였으며 주제어기에 PLL 보상기를 추가하여 출력 전압의 정상상태 성능을 개선하였다. 제안된 방법의 타당성을 검증하기 위하여 시뮬레이션과 실험을 수행하였으며, 그 결과 기존의 방법에 비해 정상상태 전압제어 성능과 Total Harmonic Distortion(THD)이 현저히 개선됨을 입증할 수 있었다.

• Journal of Power Electronics
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• 제16권5호
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• Journal of Power Electronics
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• 제16권2호
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• pp.704-716
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• 2016

Small distributed generation units are usually connected to the main electric grid through single-phase voltage source inverters. Grid operating conditions such as voltage and frequency are not constant and can fluctuate within the range values established by international standards. Furthermore, the requirements in terms of power factor correction, total harmonic distortion, and reliability are getting tighter day by day. As a result, the implementation of reliable and efficient control algorithms, which are able to adjust their control parameters in response to changeable grid operating conditions, is essential. This paper investigates the configuration topology and control algorithm of a single-phase inverter with the purpose of achieving high performance in terms of efficiency as well as total harmonic distortion of the output current. Accordingly, a Second Order Generalized Integrator with a suitable Phase Locked Loop (SOGI-PLL) is the basis of the proposed current and voltage regulation. Some practical issues related to the control algorithm are addressed, and a solution for the control architecture is proposed, based on resonant controllers that are continuously tuned on the basis of the actual grid frequency. Further, intentional islanding operation is investigated and a possible procedure for switching from grid-tied to islanding operation and vice-versa is proposed.

• 전력전자학회논문지
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• 제22권4호
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• pp.285-296
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• 2017

This paper proposes an improved modulation scheme for the medium voltage modular multi-level converter (MMC), which operates in the nearest level control and applies in the medium voltage direct current (MVDC) system. In the proposed modulation scheme, the offset (neutral-to-zero output) voltage is adjusted, with the phase voltage magnitude, thereby maintaining a constant value with N+1 level in the controllable modulation index (MI) range. In order to confirm the proposed scheme's validity, computer simulations for the 22.9 kV - 25 MVA MMC were performed with PSCAD/EMTDC, as well as hardware experiments for the 380 V - 10 kVA MMC. The proposed modulation scheme offers to build a constant pole voltage regardless of the MI value, and to build a phase voltage with improved total harmonic distortion (THD).

• Journal of Power Electronics
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• 제17권5호
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• pp.1137-1149
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• 2017

In order to reduce the cost, improve the efficiency and simplify the complicated control of existing isolated LED drivers, an improved boundary conduction mode (BCM) Buck ac-dc light emitting diode (LED) driver with extended output voltage and low total harmonic distortion is proposed. With a coupled inductor winding and a stacked output, its output voltage can be elevated to a much higher value when compared to that of the conventional Buck ac-dc converter, without sacrificing the input harmonics and power factor. Therefore, the proposed Buck LED driver can meet the IEC61000-3-2 (Class C) limitation and has a low THD. The operating principle of the topology and the design methodology of the ac-dc LED driver are presented. A 150 W ac-dc prototype was built in the laboratory and it shows that the input current harmonics meet the lighting standard. In addition, the THD is less than 16% at a typical ac input. The peak efficiency is higher than 96.5% at a full load and a normal input.

• Journal of Power Electronics
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• 제16권1호
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• Journal of Power Electronics
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• 제14권4호
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• pp.704-711
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• 2014

This paper proposes a combined fuzzy adaptive sliding-mode voltage controller (FASVC) for a three-phase UPS inverter. The proposed FASVC encapsulates two control terms: a fuzzy adaptive compensation control term, which solves the problem of parameter uncertainties, and a sliding-mode feedback control term, which stabilizes the error dynamics of the system. To extract precise load current information, the proposed method uses a conventional load current observer instead of current sensors. In addition, the stability of the proposed control scheme is fully guaranteed by using the Lyapunov stability theory. It is shown that the proposed FASVC can attain excellent voltage regulation features such as a fast dynamic response, low total harmonic distortion (THD), and a small steady-state error under sudden load disturbances, nonlinear loads, and unbalanced loads in the existence of the parameter uncertainties. Finally, experimental results are obtained from a prototype 1 kVA three-phase UPS inverter system via a TMS320F28335 DSP. A comparison of these results with those obtained from a conventional sliding-mode controller (SMC) confirms the superior transient and steady-state performances of the proposed control technique.

• 전력전자학회논문지
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• 제11권6호
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• pp.520-528
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• 2006

동일한 변압기를 사용하는 공통암 타입의 절연형 다중레벨 인버터에서 스위칭 주파수를 저감하기 위해 새로운 위상변위제어기법을 제안 하였다. 제안된 스위칭 방식은 인버터의 각 암이 기본주파수당 한번만을 스위칭을 하는 스텝 펄스파 방식을 사용하여 동일한 스위칭 주파수를 유지할 수 있다. 제안된 스위칭 방식의 타당성을 검증하기 위해 기존의 동일변압기를 이용한 멀티레벨 인버터의 스위칭 패턴과 제안된 위상변위 제어방식을 이용한 멀티레벨 인버터의 스위칭 패턴을 시뮬레이션하고 실험을 통해 비교 하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.652-654
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• 2016

본 논문에서는 FPGA를 활용하여 SVPWM (Space Vector Pulse Width Modulation)방식의 정현파 BLDC 모터 구동 로직을 설계 및 구현하였다. Hall sensor를 이용한 BLDC 모터 구동 회로는 정현파 PWM 생성회로, 데드타임 회로 및 리드 앵글 생성 회로 등으로 구성 된다. 특히 PWM 생성 회로는 SVPWM방식을 이용하여 기존 정현파 PWM 대비 선형구간이 15.5% 증가된다. 설계한 회로는 VHDL을 이용하여 모의실험 하였으며 Xilinx Spartan-6 FPGA보드를 통하여 회로의 동작 및 성능을 검증하였다. 검증 결과 모터구동 전류의 THD (Total Harmonic Distortion)은 19.32% 로 기존 정현파 구동 회로 대비 우수한 특성을 보였으며 회전자 분해능은 $1.6^{\circ}$로 정밀 제어가 가능함을 확인하였다.