• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2207-2209
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• 1997

This Paper Presents the design automation for isolated DC-DC converters. Isolated DC-DC converts have many advantages such as protection, wide range variation, and multiple output. Prosedures consist of several steps. There are the selection of converter topology, the selection of switching devices. the calculation for the value of inductances and capacitances, and the design of transformers. We verified it with many practical examples from databooks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.873-876
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• 1999

A variable gain amplifier(VGA) for wireless LAN is designed using active feedback. The amplifier is controlled by the gate voltage in the feedback path. This amplifier has more than 30㏈ gain variation and a improved linearity in the RF receiver block as input voltage increases. An active feedback topology is used by P-HEMT and is also analyzed for FET equivalent model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.37-50
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• 2009

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.

• 정보처리학회논문지C
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• 제12C권1호
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• pp.105-110
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• 2005

멀티미디어 그룹 애플리케이션들이 증가함에 따라, QoS 요구사항을 만족하는 멀티캐스트 트리를 생성하는 것은 매우 중요한 문제로 부각되고 있다. 본 논문에서는 NP-complete ans제인 지연시간 제한과 지연변이 제한을 만족하는 멀티캐스트 트리(DVBMT : delay- and delay variation-bounded multicast tree) 문제를 다루겠다. 이 문제는 목적노드들을 포함하는 신장 트리를 생성하는 것으로, 이들 목적노드들은 최소화된 멀티캐스트 지연변이를 가지며, 시작노드에서 각 목적노트로의 경로상의 지연시간은 제한된 지연시간을 만족한다. 이러한 문제의 해법은 온라인 게임이나 쇼핑, 또는 원격 회의와 같은 실시간 통신 서비스를 제공하는데 필요하다. 지금까지 DVBMT 문제를 이상적으로 다루었다고 알려진 DDVCA보다 본 논문에서 제시한 알고리즘이 더욱 효율적이라는 것은 성능 평가를 통해 확인할 수 있다. 이를 통해 확인된 성능 향상은 DDVCA를 normalized surcharge로 계산 했을 때, 약 $3.6{\%}$에서 $11.1{\%}$에 이른다. 본 논문에서 제안한 알고리즘의 시간복잡도는 $O(mn^2)$이다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.231-234
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• 2003

This paper presents a novel high frequency transformer linked full-bridge type soft-switching phase-shift PWM control scheme DC-DC power converter, which can be used as power conditioner fur small-scale fuel cell power generation system. Using full-bridge soft-switching DC-DC converter topology makes possible to use low voltage high performance MOSFETs to achieve high efficiency of the power conditioner. A tapped inductor filter is implemented in the proposed soft-switching converter topology to achieve soft-switching PWM constant high frequency operation for a wide load variation range. to minimize circulating and idling currents without using additional resonant circuit and auxiliary power switching devices. The practical effectiveness of the proposed soft-switching DC-DC converter is verified in laboratory level experiment with 1 kW 100kHz breadboard setup using power MOSFETs. Actual efficiency of 94-96$\%$ is obtained for the wide load range

• ETRI Journal
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• 제32권5호
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• pp.713-721
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• 2010

E-textile technology has earned a great deal of interest in many fields; however, existing wearable network protocols are not optimized for use with conductive yarn. In this paper, some of the basic properties of conductive textiles and requirements on wearable personal area networks (PANs) are reviewed. Then, we present a wearable personal network (WPN), which is a four-layered wearable PAN using bus topology. We have designed the WPN to be a lightweight protocol to work with a variety of microcontrollers. The profile layer is provided to make the application development process easy. The data link layer exchanges frames in a master-slave manner in either the reliable or best-effort mode. The lower part of the data link layer and the physical layer of WPN are made of a fabric serial-bus interface which is capable of measuring bus signal properties and adapting to medium variation. After a formal verification of operation and performances of WPN, we implemented WPN communication modules (WCMs) on small flexible printed circuit boards. In order to demonstrate the behavior of our WPN on a textile, we designed a WPN tutorial shirt prototype using implemented WCMs and conductive yarn.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2335-2343
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• 2018

This paper proposes an optimal damping control algorithm of the DTI (Direct Two-level Inverter) to miniaturize and reduce the weight of auxiliary power supply for railway vehicles. The conventional auxiliary power supply for railway vehicles uses a DC-DC converter to maintain the inverter input power from the line voltage smoothly. The proposed topology does not use a DC-DC converter for reducing of manufacturing and maintenance costs. It also proposes a DTI topology removed damping resistors that generate ground signal noise in a certain period. At this time, a resonance phenomenon of DC-link voltage occurs due to variation of the inductive load, and a method of controlling the resonance phenomenon of DC-link voltage is required. In order to suppress the resonance phenomenon of the DC-link voltage, at a point before resonance occurs, this paper introduces an algorithm to suppress the resonance phenomenon of DC-link voltage by compensating the resonance component of the q axis voltage of the synchronous reference frame. The proposed algorithm verifies the effect through simulation and experiment.

• Steel and Composite Structures
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• 제15권5호
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• pp.519-538
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• 2013

The design optimization of a cold-formed steel portal frame building is considered in this paper. The proposed genetic algorithm (GA) optimizer considers both topology (i.e., frame spacing and pitch) and cross-sectional sizes of the main structural members as the decision variables. Previous GAs in the literature were characterized by poor convergence, including slow progress, that usually results in excessive computation times and/or frequent failure to achieve an optimal or near-optimal solution. This is the main issue addressed in this paper. In an effort to improve the performance of the conventional GA, a niching strategy is presented that is shown to be an effective means of enhancing the dissimilarity of the solutions in each generation of the GA. Thus, population diversity is maintained and premature convergence is reduced significantly. Through benchmark examples, it is shown that the efficient GA proposed generates optimal solutions more consistently. A parametric study was carried out, and the results included. They show significant variation in the optimal topology in terms of pitch and frame spacing for a range of typical column heights. They also show that the optimized design achieved large savings based on the cost of the main structural elements; the inclusion of knee braces at the eaves yield further savings in cost, that are significant.