• Journal of Power Electronics
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• v.7 no.2
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• pp.146-158
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• 2007

A multi-pulse GTO based voltage source converter (VSC) topology together with a fundamental frequency switching mode of gate control is a mature technology being widely used in static synchronous compensators (STATCOMs). The present practice in utility/industry is to employ a high number of pulses in the STATCOM, preferably a 48-pulse along with matching components of magnetics for dynamic reactive power compensation, voltage regulation, etc. in electrical networks. With an increase in the pulse order, need of power electronic devices and inter-facing magnetic apparatus increases multi-fold to achieve a desired operating performance. In this paper, a competitive topology with a fewer number of devices and reduced magnetics is evolved to develop an 18-pulse, 2-level $\pm$ 100MVAR STATCOM in which a GTO-VSC device is operated at fundamental frequency switching gate control. The inter-facing magnetics topology is conceptualized in two stages and with this harmonics distortion in the network is minimized to permissible IEEE-519 standard limits. This compensator is modeled, designed and simulated by a SimPowerSystems tool box in MATLAB platform and is tested for voltage regulation and power factor correction in power systems. The operating characteristics corresponding to steady state and dynamic operating conditions show an acceptable performance.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.115-124
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• 2017

This paper aims to develop an SMPS topology for handling a high range of input voltages based on a DC-DC flyback converter circuit. For this purpose, 2 capacitors of the same specifications were serially connected on the input terminal side, with a flyback converter of the same circuit configuration serially connected to each of them, so as to achieve high input voltage and an effect of dividing input voltage. The serially connected flyback converters have the transformer turn ratio of 1:1, so that each coil is used for the winding of a single transformer, which is a characteristic of doubly-fed configuration and enables the correction of input capacitor voltage imbalance. In addition, a pulse transformer was designed and fabricated in a way that can achieve the isolation and noise robustness of the PWM output signal of the PWM controller that applies gate voltage to individual flyback converter switches. PSIM simulation was carried out to verify such a structure and confirm its feasibility, and a 100W class stack was fabricated and used to verify the feasibility of the proposed high voltage SMPS topology.

• Journal of Power Electronics
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• v.8 no.3
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• pp.259-267
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• 2008

Power quality improvement in a three-phase four-wire system is achieved using a new topology of DSTATCOM (distribution static compensator) consisting of a star/delta transformer with a tertiary winding and a three-leg VSC (voltage source converter). This new topology of DSTATCOM is proposed for power factor correction or voltage regulation along with harmonic elimination, load balancing and neutral current compensation. A tertiary winding is introduced in each phase for a delta connected secondary in addition to the star-star windings and this delta connected winding is responsible for neutral current compensation. The dynamic performance of the proposed DSTATCOM system is demonstrated using MATLAB with its Simulink and Power System Blockset (PSB) toolboxes under varying loads. The capacitor supported DC bus of the DSTATCOM is regulated to the reference voltage under varying loads.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.419-421
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• 1997

Three-phase system has many problems because of the unbalance load. So we propose two control algorithms using active power filter to dissolve these problems. One is three-leg inverter topology in which ac neutral line is connected directly to the midpoint of two series dc capacitors. The other is four-leg inverter topology in which ac neutral line is provided through a fourth leg. The three-phase unbalance is considered by connecting the load to one-phase. It is show that the proposed control algorithms give good performances.

• Journal of Power Electronics
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• v.12 no.2
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• pp.258-267
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• 2012

An interleaved single-stage AC/DC converter with a boost converter and an asymmetrical half-bridge topology is presented to achieve power factor correction, zero voltage switching (ZVS) and load voltage regulation. Asymmetric pulse-width modulation (PWM) is adopted to achieve ZVS turn-on for all of the switches and to increase circuit efficiency. Two ZVS half-bridge converters with interleaved PWM are connected in parallel to reduce the ripple current at input and output sides, to control the output voltage at a desired value and to achieve load current sharing. A center-tapped rectifier is adopted at the secondary side of the transformers to achieve full-wave rectification. The boost converter is operated in discontinuous conduction mode (DCM) to automatically draw a sinusoidal line current from an AC source with a high power factor and a low current distortion. Finally, a 240W converter with the proposed topology has been implemented to verify the performance and feasibility of the proposed converter.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.31 no.2
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• pp.97-104
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• 2018

In this study, a structure satisfying the fatigue constraint is designed by applying the topology optimization based on the phase field design method. In order to predict life based on the stress value, high cycle fatigue failure theory in which stress acts within the range of elastic limit is discussed and three fatigue theories of modified-Goodman, Smith-Watson-Topper and Gerber theory are applied. To calculate the global maximum stress, a modified P-norm stress correction method is used. As a result, it is possible to obtain topology optimization results that minimize the volume while satisfying the fatigue constraints. By applying the phase field design method, a simple shape with a minimized gray scale was obtained, and the maximum stress value acting on the optimization result became very close to the allowable stress value due to the modified P-norm stress method. While previous studies does not consider the stress correction factor, this study proposes the determination method regarding the stress correction factor considering loading effects related to axial stress components.

• Journal of Power Electronics
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• v.6 no.4
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• pp.330-339
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• 2006

This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for ($2{\times}36$ Watt) fluorescent lamps operating at 50 kHz switching frequency and input line voltage (230 V, 50 Hz).

• Journal of Power Electronics
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• v.15 no.3
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• pp.644-651
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• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.363-364
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• 2016

In this paper, a novel bridgeless interleaved power factor correction circuit with single current sensor is proposed. The proposed control strategy requires only one current sensor for the interleaved bridgeless PFC. By sampling the output current, all the boost indictor currents can be calculated and used to control the input current according to the input voltage. The reduced number of current sensors and associated feedback circuits helps reduce the cost of system. The problem caused by the unequal current gain between current sensors inherently does not exist in the proposed topology. Thus, current sharing between converters can be achieved more accurately and the high frequency distortion is decreased. In addition, the proposed technique can be applied to the other kinds of interleaved PFC topologies. Performance of the proposed control strategy is verified by the experimental results with 6.6kW bridgeless interleaved PFC circuit.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.639-642
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• 1999

An integrated zero current switching(ZCS) quasi-resonant converter(QRC) for power factor correction and high efficiency with single switch is proposed in this thesis. Boost integrated circuit operating discontinuous conduction mode(DCM) and QRC are used for power factor correction and reducing switching loss, respectively. A prototype converter has been designed and experimented. At rated condition, the THD in the input current waveform of this prototype has approximately 18%. The efficiency is obtained about 70%, the power factor is about 0.985 as well. Therefore, the proposed converter is suitable for a low power level converter with operating switching frequency above several hundred KHz.