• Title/Summary/Keyword: Topology Processor

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Single-Phase Step-Up Five-Level Inverter with Phase-Shifted Pulse Width Modulation

  • Chen, Jianfei;Wang, Caisheng;Li, Jian
    • Journal of Power Electronics
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    • v.19 no.1
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    • pp.134-145
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    • 2019
  • A single-phase step-up five-level inverter topology with a new phase-shifted pulse width modulation (PS-PWM) strategy is proposed in this paper. When compared with conventional single-phase five-level inverter topologies, the proposed topology can realize multilevel inversion with a double step-up ratio, a reduced number of switching devices and self-balanced capacitor voltages. When compared with the conventional PS-PWM strategy, the new PS-PWM strategy can be implemented with one carrier reduced, which makes it much easier to implement in a digital signal processor (DSP) system. Experimental results have been presented to verify the effectiveness of the proposed inverter and the PS-PWM strategy.

Distributed Kinetic Delaunay Triangulation

  • Yoo Taewon;Choi Sunghee;Lee Hyonik;Lee Jinwon
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.11a
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    • pp.964-966
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    • 2005
  • This paper proposes a distributed algorithm to maintain the Delaunay triangulation of moving points. We assume that every point is a processor which can only communicate with the adjacent points connected by edges in the Delaunay triangulation. The topology changes of the Delaunay triangulation due to the movement of the points are updated automatically by local operations of the points without any centralized processor or global information.

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Parallel Performance of Preconditioned Navier-Stokes Code on Myrinet Environment (Myrinet 환경에서 예조건화 Navier-Stokes 코드의 병렬처리 성능)

  • Kim M.-H.;Lee G. S.;Choi J.-Y.;Kim K. S.;Kim S.-L.;Jeung I.-S.
    • 한국전산유체공학회:학술대회논문집
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    • 2001.05a
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    • pp.149-154
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    • 2001
  • Parallel performance of a Myrinet based PC-cluster was tested and compared with a conventional Fast-Ethernet system. A preconditioned Navier-Stokes code was parallelized with domain decomposition technique, and used for the parallel performance test. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network topology. As was expected, Myrinet system shows a superior parallel performance to the Fast-Ethernet system even with a single network adpater for a dual processor SMP machine. A test for the dependency on problem size also shows that network communication speed is a crucial factor for parallelized computational fluid dynamics analysis and the Myrinet system is a plausible candidate for high performance parallel computing system.

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An Energy-Efficient Self-organizing Hierarchical Sensor Network Model for Vehicle Approach Warning Systems (VAWS) (차량 접근 경고 시스템을 위한 에너지 효율적 자가 구성 센서 네트워크 모델)

  • Shin, Hong-Hyul;Lee, Hyuk-Joon
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.7 no.4
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    • pp.118-129
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    • 2008
  • This paper describes an IEEE 802.15.4-based hierarchical sensor network model for a VAWS(Vehicle Approach Warning System) which provides the drivers of vehicles approaching a sharp turn with the information about vehicles approaching the same turn from the opposite end. In the proposed network model, a tree-structured topology, that can prolong the lifetime of network is formed in a self-organizing manner by a topology control protocol. A simple but efficient routing protocol, that creates and maintains routing tables based on the network topology organized by the topology control protocol, transports data packets generated from the sensor nodes to the base station which then forwards it to a display processor. These protocols are designed as a network layer extension to the IEEE 802.15.4 MAC. In the simulation, which models a scenario with a sharp turn, it is shown that the proposed network model achieves a high-level performance in terms of both energy efficiency and throughput simultaneously.

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Buck-Flyback (fly-buck) Stand-Alone Photovoltaic System for Charge Balancing with Differential Power Processor Circuit

  • Lee, Chun-Gu;Park, Jung-Hyun;Park, Joung-Hu
    • Journal of Power Electronics
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    • v.19 no.4
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    • pp.1011-1019
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    • 2019
  • In this paper, a buck-flyback (fly-buck) stand-alone photovoltaic (PV) system for charge balancing with a differential power processor (DPP) circuit is proposed. Conventional feed-back DPP converters draw differential feed-back power from the output of a string converter. Therefore, the power is always through the switches and diodes of the string converter. Because of the returning conduction path, there are always power losses due to the resistance of the switch and the forward voltage of the diode. Meanwhile, the proposed feed-back DPP converter draws power from the magnetically-coupled inductor in a string converter. This shortens the power path of the DPP converter, which reduces the power losses. In addition, the extra winding in the magnetically-coupled inductor works as a charge balancer for battery-stacked stand-alone PV systems. The proposed system, which uses a single magnetically-coupled inductor, can control each of the PV modules independently to track the maximum power point. Thus, it can overcome the power loss due to the power path. It can also achieve charge balancing for each of the battery modules. The proposed topology is analyzed and verified using 120W hardware experiments.

Investigation to Metal 3D Printing Additive Manufacturing (AM) Process Simulation Technology (II) (금속 3D 프린팅 적층제조(AM) 공정 시뮬레이션 기술에 관한 고찰(II))

  • Kim, Yong Seok;Choi, Seong Woong;Yang, Soon Yong
    • Journal of Drive and Control
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    • v.16 no.3
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    • pp.51-58
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    • 2019
  • The objective of this study was to investigate a simulation technology for the AM field based on ANSYS Inc.. The introduction of metal 3D printing AM process, and the examining of the present status of AM process simulation software, and the AM process simulation processor were done in the previous study (part 1). This present study (part 2) examined the use of the AM process simulation processor, presented in Part 1, through direct execution of Topology Optimization, Ansys Workbench, Additive Print and Additive Science. Topology Optimization can optimize additive geometry to reduce mass while maintaining strength for AM products. This can reduce the amount of material required for additive and significantly reduce additive build time. Ansys Workbench and Additive Print simulate the build process in the AM process and optimize various process variables (printing parameters and supporter composition), which will enable the AM to predict the problems that may occur during the build process, and can also be used to predict and correct deformations in geometry. Additive Science can simulate the material to find the material characteristic before the AM process simulation or build-up. This can be done by combining specimen preparation, measurement, and simulation for material measurements to find the exact material characteristics. This study will enable the understanding of the general process of AM simulation more easily. Furthermore, it will be of great help to a reader who wants to experience and appreciate AM simulation for the first time.

Bidirectional Power Conversion of Isolated Switched-Capacitor Topology for Photovoltaic Differential Power Processors

  • Kim, Hyun-Woo;Park, Joung-Hu;Jeon, Hee-Jong
    • Journal of Power Electronics
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    • v.16 no.5
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    • pp.1629-1638
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    • 2016
  • Differential power processing (DPP) systems are among the most effective architectures for photovoltaic (PV) power systems because they are highly efficient as a result of their distributed local maximum power point tracking ability, which allows the fractional processing of the total generated power. However, DPP systems require a high-efficiency, high step-up/down bidirectional converter with broad operating ranges and galvanic isolation. This study proposes a single, magnetic, high-efficiency, high step-up/down bidirectional DC-DC converter. The proposed converter is composed of a bidirectional flyback and a bidirectional isolated switched-capacitor cell, which are competitively cheap. The output terminals of the flyback converter and switched-capacitor cell are connected in series to obtain the voltage step-up. In the reverse power flow, the converter reciprocally operates with high efficiency across a broad operating range because it uses hard switching instead of soft switching. The proposed topology achieves a genuine on-off interleaved energy transfer at the transformer core and windings, thus providing an excellent utilization ratio. The dynamic characteristics of the converter are analyzed for the controller design. Finally, a 240 W hardware prototype is constructed to demonstrate the operation of the bidirectional converter under a current feedback control loop. To improve the efficiency of a PV system, the maximum power point tracking method is applied to the proposed converter.

New Single-Phase Power Converter Topology for Frequency Changing of AC Voltage

  • Jou, Hurng-Liahng;Wu, Jinn-Chang;Wu, Kuen-Der;Huang, Ting-Feng;Wei, Szu-Hsiang
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.694-701
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    • 2018
  • This paper proposes a new single-phase power converter topology for changing the frequency of AC voltage. The proposed single-phase frequency converter (SFC) includes a T-type multi-level power converter (TMPC), a frequency decoupling transformer (FDT) and a digital signal processor (DSP). The TMPC can convert a 60 Hz AC voltage to a DC voltage and then convert the DC voltage to a 50 Hz AC voltage. Therefore, the output currents of the two T-type power switch arms have 50 Hz and 60 Hz components. The FDT is used to decouple the 50 Hz and 60 Hz components. The salient feature of the proposed SFC is that only one power electronic converter stage is used since the functions of the AC-DC and DC-AC power conversions are integrated into the TMPC. Therefore, the proposed SFC can simplify both the power circuit and the control circuit. In order to verify the functions of the proposed SFC, a hardware prototype is established. Experimental results verify that the performance of the proposed SFC is as expected.

Design and Simulation of Interconnection Network Based on Topological Combination (위상 결합을 기반으로 한 연결 망 설계 및 시뮬레이션)

  • 장창수;최창훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.6B
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    • pp.563-574
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    • 2004
  • In this paper, we propose a new class of MIN(Multistage Interconnection Network) called Combine MIN which combines static network topology and apimic network topology. Combine U provides multiple paths at a hardware cost lower than that of MIN with unique path property. Combine MIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. According to the results of analysis and simulation for performance evaluation, Combine MIN shows higher performance than MINs of the same network size in the highly localized communication Therefore, Combine MIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

Development of the Contingency Analysis Program of Korean Energy Management System (한국형 에너지 관리시스템용 상정고장 해석프로그램 개발)

  • Cho, Yoon-Sung;Yun, Sang-Yun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.2
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    • pp.232-241
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    • 2010
  • This paper describes the development of robust contingency analysis program for Korean Energy Management System. The important function of contingency analysis is to determine the bus/branch model for contingency, and to calculate the state of the power network based on the network model and topology output. In the proposed method, the bus/branch models for contingencies are determined exactly using a fast linked-list method based on the application common model database. To calculate the state of the power system included contingency, the full-decoupled powerflow approach, the partial powerflow method for contingencies and the proposed contingency screening algorithm are also used to contingency analysis. To verify the performance of the developed processor, we performed a file-based test using several structured input data and online test using the database which resides on memory. The results of these comprehensive tests showed that the developed processors can accurately calculate the power system contingency state from online data and can be applied to Korea Power Exchange system.