• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2009년도 제40회 하계학술대회
• /
• pp.1342_1342
• /
• 2009

Zinc tin oxide (ZTO) based thin-film transistors (TFTs) were fabricated on glass substrate by using sol-gel method. The fabricated ZTO TFT had bottom gate and top contact structure with ZTO layer formed by spin coating from ZTO solution. The fabricated TFT showed field-effect mobility of about 2 - $4\;cm^2/V{\cdot}s$ with on/off current ratios >$10^7$, and threshold voltage of 2 V.

• 기술사
• /
• 제14권4호
• /
• pp.15-25
• /
• 1981

Electrical behaviors of the divalent silver oxide-zinc cell were analyzed for imporving capacity and keeping electrodes from passivation or sharp increases of cell internal resistance in the course of discharge. One of primary factors in relation to lowering performance can be depicted by cell internal resistance increase being created by various routes, first by insufficiency and/or the carbonation of the electrolyte, secondly by barrier blockage, thirdly by electrode passivation which are due to improper material use of wrong processing, and by gassing as fourth cause. The carbonation causes electrobyte to have impedance up as well as poor amalgamation, resulting in vigorous corrosion reaction of copper plated inner top, evolving hydrogen gas. Electrical characteristics of the cell was reviewed to elucidate relationships between the discharge capacity and the cell internal resistance.

• 한국세라믹학회지
• /
• 제55권2호
• /
• pp.174-177
• /
• 2018

ZnO/Ag/ZnO multilayers were fabricated and their optical properties were investigated in terms of the micro-cavity effect in electroluminescent devices based on colloidal quantum dots. The top and bottom ZnO layers were formed by a sol-gel method while the middle Ag layer was deposited by thermal evaporation. After the fabrication of the ZnO/Ag/ZnO structure, the transmittance increased to 74%. When the oxide/metal/oxide multilayers were applied to quantum dot light-emitting diodes, the color purity was enhanced due to the narrower full width at half maximum.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.56-56
• /
• 2008

ZnO Oxide TFT with organic dielectric was prepared. ZnO thin film as active channel was prepared by plasma enhanced atomic deposition technique. Organic dielectric was spin coated on the gate metal. The structure of prepared TFT is bottom gate type and top contact structure. The characterization of oxide TFT was performed. We obtained the mobility of $0.7cm^2$/Vs, the threshold voltage of -14V, and the on-off ratio of $10^4$. We also obtained good output characterization with solid saturation.

• 센서학회지
• /
• 제16권3호
• /
• pp.229-233
• /
• 2007

The indium tin oxide (ITO) films were deposited on CR39 substrate using DC magnetron sputtering. The ITO thin films deposited at room temperature because CR39 substrate its glass-transition temperature is $130^{\circ}C$. The ITO thin films used bottom and top electrode and for organic thin film transparent transistors (OTFTs). The ITO thin film electrodes electrical properties and optical transparency properties in the visible wavelength range (300-800 nm) strongly dependent on volume of oxygen percent. For the optimum resistivity and transparency of the ITO thin film electrode achieved with a 75 W plasma power, 10 % volume of oxygen and a 27 nm/min deposition rate. Above 85 % transparency in the visible wavelength range (300-800 nm) measured without post annealing process and a low resistivity value $9.83{\times}10^{-4}{\Omega}cm$ was measured thickness of 300 nm. All fabrication process of ITO thin films did not exceed $80^{\circ}C$.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
• /
• pp.127-129
• /
• 1994

For scale-down EEPROM, MONOS structures with the different thicknesses of gate insulators, are fabricated and the memory characteristics, such as swtching and retention characteristics are investigated. As a results, the devices with the top oxide of 20A thick were deteriorated in retentivity. However, 11V-programmable voltage for ΔV$\sub$FB/=4V and 10-year data retention were achieved in MONOS structure with the t7p oxide of 50 ${\AA}$ thick and nitride 45${\AA}$thick.

• Transactions on Electrical and Electronic Materials
• /
• 제3권3호
• /
• pp.14-17
• /
• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• 대한금속재료학회지
• /
• 제46권1호
• /
• pp.39-43
• /
• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• 대한전자공학회논문지
• /
• 제4권1호
• /
• pp.3-12
• /
• 1967

증기반응법에 의한 산화석금속피막저항기(Tin Oxide Film Resistor)의 제법을 연구하고 이방법을 이용하여 제조한 저항피막의 전기적 성질을 관찰하였다. 이때 봉상의 파이렉스 유리(Pyrex glass rod) 표면에 산화석피막을 입혔다. 이 방법은 균질한 저항피막을 쉽게 얻을 수 있고, 진공계를 필요하지 않으므로 대량생산에 적합한 제법의 기초가 된다고 할수 있다. 본제법에 의하여 만든 제품중 표면저항 25ohm/sq에서 저항온도계수(T.C.R) 12ppm을 얻었다.

• 한국재료학회지
• /
• 제19권9호
• /
• pp.473-480
• /
• 2009

In order to provide the mechanism of nozzle clogging, recovered nozzles for high strength steel grade were examined carefully after continuous casting. The thickness of clogged material in SEN is increased in the following order: from the bottom to the top of the nozzle, upper part of slag line, and the pouring hole. Nozzle clogging material begins to form due the adhesion of metal to nozzle wall, the decarburization, and reduction of oxide in the refractory by Al and Ti in the melt. The reduction of oxide in the refractory by Al and Ti improves the wettability of the melt on the refractory and forms a thin Al-Ti-O layer. Metal containing micro alumina inclusions is solidified on the Al-Ti-O layer, and the solid layer grows due to the heat evolution through the nozzle wall. Thermodynamic calculation has been made for the related reactions. The effect of superheat to the nozzle clogging is discussed on ultra low carbon steel and low carbon steel.