• Applied Chemistry for Engineering
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• v.10 no.3
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• pp.354-361
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• 1999

The films annealed after physical deposition of titanium and chemical deposition of amorphous silicon by plasma were formed Si-rich titanium silicide with a good quality of crystallinity and had the various lattice structures due to orientation of lattices for epitaxy growth during annealing process. Band gap of the titanium silicide had 1.14~1.165 eV and the films annealed after chemical deposition of a-Si:H by plasma were influenced by a-Si and the dangling bond offered by desorption of hydrogen. Urbach tail ($E_0$) of the films annealed after physical deposition of Ti was nearly constant within a range of 0.045~0.05 eV, and the number of defect in films annealed after chemical deposition of a-Si:H by plasma was about 2~3 times more than that in annealed Ti/Si films.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Proceedings of the Materials Research Society of Korea Conference
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• 1992.05b
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• pp.159-160
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• 1992

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.153-161
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• 1992

A plasma has been used in a high vaccum, cold wall reactor for low temperature deposition of C54 TiSi2 and for in-situ surface cleaning prior to silicide deposition. SiH4 and TiCl4 were used as the silicon and titanium sources, respectively. The deposited films had low resistivities in the range of 15~25 uohm-cm. The investigation of the experimental variables' effects on the growth of silicide and its concomitant silicon consumption revealed that and were the dominant species for silicide formation and the primary factors in silicon consumption were gas composition ratio and temperature. Increasing silane flow rate from 6 to 9 sccm decreased silicon consumption from 1500 A/min to less than 30 A/min. Furthermore, decreasing the temperature from 650 to $590^{\circ}C$ achieved blanket silicide deposition with no silicon consumption. A kinetic model of silicon consumption is proposed to understand the fundamental mechanism responsible for the dependence of silicon consumption on SiH4 flow rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.1-9
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• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.57-62
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• 1989

Sputter-deposited Ti film on Si substrates which were implanted with various doses of As was annealed at the temperature of 600-900$^{circ}C$ for 20 sec in Ar atmosphere. The sheet resistance of Ti-silicides was measured by 4-point probe, the thickness by $alpha$-step, and observed the behavior of As dopant in Si substrates by ASR. With increasing As doses, the thickness of Ti-silicides decreased and the sheet resistance of Ti-silicides increased. And we discussed the relationships between the above results and the factors of Si diffusion.

• Analytical Science and Technology
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• v.5 no.2
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• pp.199-202
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• 1992

Ti-silicide was formed by using metal-Ti target and composite target on the silicon substrate that $BF_2$ were introduced into. Implant energies of $BF_2$ were 50keV and 90keV. The behavior of boron was investigated by SIMS. The redistribution of boron occurred during the formation of Ti-silicide by metal-Ti target and the sample implanted at the energy of 50keV showed severe out-diffusion. In the case that Ti-silicide was formed by composite target, there was little redistribution of boron.

• Analytical Science and Technology
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• v.5 no.3
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• pp.303-308
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• 1992

Initial reactions of Ti and Si have been studied to examine the surface roughness of titanium silicide. Formation mechanism has been explored with in-situ measurement tools such as AES(Auger electron spectroscopy) and LEED (low energy electron diffraction). One or two monolayers of Ti films have been deposited in ultrahigh vacuum on atomically clean Si(111) substrates. Atomically clean Si substrates which are reconstructed $7{\times}7$ Si(111) have been obtained after in-situ heat cleaning in ultrahigh vacuum. Deposition of the films were monitored by a quartz cuystal oscillator and the Ti films were analyzed with in-situ AES and LEED. The in-situ measurements show that the initial reactions of Ti and Si occur at room temperature and form a disordered layer. At low temperatures($200^{\circ}C{\sim}300^{\circ}C$) intermixing of Ti and Si is detected by AES. Substrate $1{\times}1$ LEED patterns are displayed after $400^{\circ}C$ anneal. This indicates that the disordered layer has transformed to form an ordered surface. The reappearance of the $7{\times}7$ LEED pattern in observed with further high temperature anneals and indicates three dimensional titanium silicide island formation.

• Korean Journal of Materials Research
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• v.13 no.11
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.