• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.05a
• /
• pp.226-230
• /
• 2000

In this paper, we implemented the QPSK demodulator with a CPLD chip, and examined the results. DD(Decision Directed)-Gardner algorithm is used for STR loop and Decision-Directed algorithm is used for CPR loop. The speed of the QPSK demodulator implemented in FLEX10K chip can be guaranteed approximately 2[Mbpsl] transmission speed. In practical designed by ASIC, the speed is faster than that of CPLD by 5-6 times.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.2
• /
• pp.417-426
• /
• 1996

The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

• Journal of the Korean Society for Aviation and Aeronautics
• /
• v.28 no.4
• /
• pp.147-153
• /
• 2020

This study analyzed the outlook for aviation demand for the recovery of the aviation industry, focusing on airlines facing difficulties in management due to the Covid-19 crisis. Although the timing of the recovery in aviation demand is uncertain at the moment, this study is based on prior research related to Covid-19 and forecasts by aviation specialists, and analyzed by SWOT technique to a group of aviation experts to derive and suggest implications for the prospects of aviation demand. Looking at the implications based on the analysis results, first, customer trust to prevent infection should be considered a top priority for recovering aviation demand. Second, promote reasonable air price policy. Finally, it seeks to try various research and analysis techniques to predict long-term aviation demand to overcome Covid-19.

• Journal of Service Research and Studies
• /
• v.6 no.3
• /
• pp.57-78
• /
• 2016

The purpose of this research is to study how service recovery activities influence customers' commodity churning in the media telecommunication industry(CATV industry). Put it differently, we tried to identify this change of commodity churning rates by the stages of service failures, by which we intend to emphasize the importance of service recoveries. Korean media telecommunication market has already been saturated; customers tend to move to bigger major companies with better customer care increasingly. As once customers gone never returns, CRM functions are being reinforced over the time. We were able to have the following results. First, turning rates, for those experienced service failure, who were dissatisfied with service recovery activities are 2~5 times (monthly average turning rates are 1.3%) higher than those satisfied. Secondly, active service recovery activities at the customer's service request after experiencing service failure lowered churning rates significantly. The most effective timing is service recovery activities pre-recovery stage. Thirdly, reward activities after service recovery activities at the immediate recovery stage is more effective than service recovery at the arranged recovery schedule and reward activities after customer's expressing churning intension. The implications of this study are that firms should engage in service recovery activities at the time of identifying service failures, prior to customer's expressing churning intention, which means relatively lower ROI for the service recovery activities than the times of customers' expressing churning intention.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.21-26
• /
• 2008

In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.10a
• /
• pp.307-310
• /
• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.8A
• /
• pp.785-793
• /
• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.66 no.1
• /
• pp.21-26
• /
• 2017

Failure of high-voltage transmission line, which is responsible for large-scale power transmission, can be reason for system voltage instability. There are many methods to prevent voltage instability like adjustment of equipment, the generator voltage setting, and load shedding. Among them, the load shedding, have a problem of economic loss and cascading effect to power system. Therefore, the execution of load shedding, amount and timing is very important. Conventionally, the load shedding setting is decided by the preformed simulation. Now, it is possible to monitor the power system in real time by the appearance of PMU(Phasor Measurement Unit). By this reason, some of research is performed about decentralized load shedding. The characteristics of the load can impact to amount and timing of decentralized load shedding. Especially, it is necessary to consider the influence of the induction motor loads. This paper review recent topic about under voltage load shedding and compare with decentralized load shedding scheme with conventional load shedding scheme. And simulations show the effectiveness of proposed method in resolving the delayed voltage recovery in the Korean Power System.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1A
• /
• pp.27-33
• /
• 2000

Gardner’s algorithm is one of the useful algorithm for NDD(Non-Decision Directed) symbol synchronization in PAM communications. But the algorithm has a weak point such as pattern noises increasing in multi-level PAM. To insert a pre-filter in the algorithm is able to reduce timing jitter and pattern noise. In this paper, we analyze statistical properties of NDD algorithm to find an optimal parameter of the pre-filter for improving timing jitter and PLL locking. As a simulation result, optimum value of pre-filter parameter, $\beta$, is 0.3 and 0.5 at the roll off factor of the channel, $\alpha$, is 0.5 and 1.0, respectively. Optimum parameters of the pre-filter for clock synchronization of all-digital 256-QAM demodulator is shown in the results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.8A
• /
• pp.771-778
• /
• 2002

We investigate the design of an interpolation filter of a MF-TDMA demodulator which is applied to DVB-RCS. If sampling is not synchronized to the data symbols, timing adjustment in digital receiver must be performed by interpolation. It is impossible that conventional sinc interpolation filter coefficients are actually extended to infinity. We propose a Kaiser window interpolation filter and a sinc interpolation filter using th Kaiser window. Simulation results show that the performance improvement is realized by employing the proposed interpolation filter.