• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.103-118
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• 1999

This paper analyzes the performance of symbol timing recovery and equalizer in 8VSB digital terrestrial TV receiver under various multipath signals and proposes equalization techniques which improve indoor reception performance. Data segment sync is used for symbol timing recovery and timing offset is measured for echoes of various delays and amplitudes by using symbol timing detection filter whose pattern is +1. +1. -1. and -1. Measured timing offsets were below 10% for long echoes with more than 5 symbol delay and above 30% for short echoes with around 1 symbol delay. Indoor reception is always more challenging than outdoor reception due to lower signal strength. large and short multipaths. and moving interfering objects. So it is considered to use FSE (Fractionally Spaced Equalizer) which is very robust to timing offset and blind equalizer which can update equalizer tap coefficients even by information data. We compare the performance of conventional DFE (Decision Feedback Equalizer) and FSE-DFE using LMS algorithm and Stop and Go algorithm for the indoor reception. Experiments reveals FSE has excellent performance for large timing offset and Stop and Go algorithm shows good performance for Doppler shift. so we propose to use FSE-DFE structure with Stop and Go algorithm for the reliable indoor reception.

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.2
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• pp.101-116
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• 2002

Modern vehicles require a high degree of refinement, including good driveability to meet customer demands. Vehicle driveability, which becomes a key decisive factor for marketability, is affected by many parameters such as engine control and the dynamic characteristics in drive lines. Therefore, Engine and drive train characteristics should be considered to achieve a well balanced vehicle response simultaneously. This paper describes analysis procedures using a mathematical model which has been developed to simulate spark timing control logic. Inertia mass moment, stiffness and damping coefficient of engine and drive train were simulated to analyze the effect of parameters which were related vehicle dynamic behavior. Inertia mass moment of engine and stiffness of drive line were shown key factors for the shuffle characteristics. It was found that torque increase rate, torque reduction rate and torque recovery timing and rate influenced the shuffle characteristics at the tip-in condition for the given system in this study.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• Journal of Power Electronics
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• v.6 no.3
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• pp.253-263
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• 2006

A high performance and low cost single switch current fed energy recovery circuit (ERC) for an alternating current (AC) plasma display panel (PDP) is proposed. Since it is composed of only one power switch compared with the conventional circuit consisting of four power switches and two large energy recovery capacitors, the ERC features a simpler structure and lower cost. Furthermore, since all power switches can be switched under soft switching operating conditions, the proposed circuit has desirable merits such as increased reliability and low switching loss. Specifically, there are no serious voltage notches across the PDP with the aid of gas discharge current compensation, which can greatly reduce the current stress of all inverter switches, and provide those switches with the turn on timing margin. To confirm the validity of proposed circuit, its operation and performance were verified on a prototype for 7-inch test PDP.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.53-58
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• 2007

OFDM (orthogonal frequency division multiplexing) is an effective modulation technique for high speed transmission over fading channels. However, it has a high bit error rate in the receiver if there is an error on frame synchronization because of phase rotation. A coherent OFDM system has to acquire exact timing synchronization of fraction and integer sampling positions. When a sampling offset exist the performance of a receiver will be degraded severely. In this paper, we propose an algorithm that acquires the fractional sampling offset in OFDM systems. This scheme compares the channel impulse responses with the early and late sampled signals having 0.5 sample offset from the estimated sampling positions by correlation with the received and training samples. Its performance is verified by computer simulations in multipath channels.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.462-462
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• 2004

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1029-1034
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• 2010

For All Digital QPSK receivers, a phase recovery scheme is required to fix the arbitrarily rotated I/Q quadrature signals due to the transmission path and clock mismatch between the transmitter and the receiver. The conventional Costas phase recovery loop scheme requires a separate AGC(Automatic Gain Control) to obtain the performance independent of input signal power. This paper proposes a simple scheme which separates the phase and amplitude of the input signal via CORDIC algorithm and performs the phase recovery and amplitude compensation simultaneously. The proposed scheme can considerably reduce the logic resources in hardware implementation, has been verified by C++ and Model Sim simulations.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.4
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• pp.22-28
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• 2013

It is important to begin left ventricular assist device (LVAD) treatment at appropriate time for heart failure patients who expect cardiac recovery after the therapy. In order to predict the optimal timing of LVAD implantation, we predicted pumping efficacy of LVAD according to the severity of heart failure theoretically. We used LVAD-implanted cardiovascular system model which consist of 8 Windkessel compartments for the simulation study. The time-varying compliance theory was used to simulate ventricular pumping function in the model. The ventricular systolic dysfunction was implemented by increasing the end-systolic ventricular compliance. Using the mathematical model, we predicted cardiac responses such as left ventricular peak pressure, cardiac output, ejection fraction, and stroke work according to the severity of ventricular systolic dysfunction under the treatments of continuous and pulsatile LVAD. Left ventricular peak pressure, which indicates the ventricular loading condition, decreased maximally at the 1st level heart-failure under pulsatile LVAD therapy and 2nd level heart-failure under continuous LVAD therapy. We conclude that optimal timing for pulsatile LVAD treatment is 1st level heart-failure and for continuous LVAD treatment is 2nd level heart-failure when considering LVAD treatment as "bridge to recovery".