• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.326-332
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• 2017

A switched VCO-based UWB transmitter for 3-5 GHz is implemented using $0.18{\mu}m$ CMOS technology. Using RF switch and timing control of DPGs, the uniform RF power and low power consumption are possible regardless of carrier frequency. And gate control of RF switch enables the undesired side lobe rejection sufficiently. The measured pulse width is tunable from 0.5 to 2 ns. The measured energy efficiency per pulse is 4.08% and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier.

• 한국자동차공학회논문집
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• 제11권2호
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• pp.89-95
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• 2003

We consider a problem of application of analytical redundancy to engine synchronization process of spark ignition engines, which is critical to timing for every ECU process including ignition and injection. The engine synchronization process we consider here is performed using the pulse signal obtained by the revolution of crankshaft trigger wheel (CTW) coupled to crank shaft. We propose a discrete-time linear model for the signal, for which we construct FDI (Fault Detection & Isolation) system consisting residual generator and threshold based on linear observer.

• 한국군사과학기술학회지
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• 제11권4호
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• pp.92-98
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• 2008

A beam steering system of X-band 2-D phased array antenna for radar application is developed. The beam steering system consists of real-time command generator, beam steering unit, control PCB of array module and power supply. It plays a role of beam steering and on-line check of phased array antenna. The performance of beam steering system is verified with pulse timing of current control in phase shifters and measurement of far-field of phased array antenna. The developed beam steering system offers basic technology to develop full-scale beam steering system of multi-function radar.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.