• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.587-588
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• 2008

Digital PLL을 위한 높은 해상도를 갖는 TDC(Time to Digital Converter)를 $0.18{\mu}m$ CMOS 공정으로 설계하였다. 2단 구조를 갖는 TDC를 제안하였고 이를 Cadence Spectre를 이용하여 검증하였다. TDC는 Difference pulse generator, coarse 변환기와 fine 변환기로 구성된다. 그리고, 2단 변환기와 Thermometer decoder를 이용하여 delay cell의 수를 적게 유지하면서도 높은 해상도를 얻을 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 정기총회 및 창립40주년기념 학술대회 학회본부
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• pp.534-538
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• 1987

State-space techniques are employed to derive an equivalent nonlinear recurrent time-domain model that describes the series resonant converter behavior exactly. This model is employed effectively to analyze large signal behavior by propagating the recurrent equation and matching boundary conditions through digital computation. The model is verified with a laboratory converter for a steady-state operation.

• Journal of Power Electronics
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• 제11권4호
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• pp.479-489
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• 2011

The bidirectional dc-dc converter, being the interface between Energy Storage Element (ESE) and DC bus, is an essential component of the power management system for vehicle applications including electric vehicle (EV), hybrid electric vehicle (HEV), and fuel cell vehicle (FCV). In this paper, a novel multiphase bidirectional dc-dc converter interfacing with battery to supply and absorb the electric energy in the FCV system was studied with the help of real time digital simulator (RTDS). The mathematical models of fuel cell, battery and dc-dc converter were derived. A power management strategy was developed and first simulated in RTDS. A Power Hardware-In-the-Loop (PHIL) simulation using RTDS is then presented. The main challenge of this PHIL is the requirement for a highly dynamic bidirectional Simulation-Stimulation (Sim-Stim) interface. This paper describes three different interface algorithms. The closed-loop stability of the resulting PHIL system is analyzed in terms of time delay and sampling rate. A prototype bidirectional Sim-Stim interface is designed to implement the PHIL simulation.

• 한국정보통신학회논문지
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• 제16권4호
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• pp.799-804
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• 2012

시간 정보를 디지털 정보로 변환하기 위한 아날로그 지연소자를 사용하는 시간-디지털 변환회로를 설계하였다. 설계된 회로는 동작 온도가 변화하더라도 안정된 출력을 얻을 수 있도록 설계하였으며, HSPICE 시뮬레이션을 통하여 동적을 확인하였다. 설계된 지연소자는 온도가 $-20^{\circ}C$에서 $70^{\circ}C$까지 변화할 때 상온에 비해 -0.18%-0.126%의 지연시간 변화율을 보였다. 그리고 이를 이용하는 시간-디지털 변환회로에서 온도가 $-20^{\circ}C$에서 $70^{\circ}C$까지 변화하고 디지털 출력 값이 15가 되었을 때의 시간을 비교하면, 상온에 비하여 -0.18%에서 0.12%의 시간차를 보였다. 그러나 온도 변화에 안정화되지 않은 시간-디지털 변환회로의 경우 상온에 비하여 -1.09%에서 1.28%의 시간차를 보였다.

• 전기학회논문지
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• 제65권12호
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• pp.2000-2007
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• 2016

Generally, in order to implement the CRM(Critical Conduction Mode), the analog controller is used rather than a digital controller because the control is simple and uses less power. However, according to the semiconductor technology development and various user needs, digital control system based on a DSP is on the rise. Therefore, in this paper, the CRM bridgeless PFC converter based on a digital control is proposed. It is necessary to detect the inductor current when it reaches zero and peak value, for calculating the on time and off time by using the current information. However, in this paper, the on-time and off-time are calculated by using the proposed algorithm without any current information. If the switching-times are calculated through the steady-state analysis of the converter, they do not reflect transient status such as starting-up. Therefore, the calculated frequency is out of range, and the transient current is generated. In order to solve these problems, limitation method of the on-time and off-time is used, and the limitation values are varied according to the voltage reference. In addition, in steady state, depending on the switching frequency, the inductance is varied because of the resonance between the inductor and the parasitic capacitance of the switching elements. In order to solve the problem, inductance are measured depending on the switching frequency. The measured inductance are used to calculate the switching time for preventing the transient current. Simulation and experimental results are presented to verify the proposed method.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 추계학술대회 논문집
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• pp.94-97
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• 2008

In this paper, A Digital Voltage Mode Controller is designed for the Photovoltaic power converter applications. The designed Digital Voltage Mode Controller is derived analytically from the continuous time small signal model of the boost converter. Due to the small signal model based derivations of the control law, the designed control method can be applicable to K-factor Approach method and bilinear transformation. In order to show the usefulness of a designed controller, and the simulation results are verified.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.794-799
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• 2005

Robust DC-DC converter which can cover extensive load changes and also input voltage changes with one controller is needed. In this paper, we propose a method for determining the parameters of 2DOF digital controller which makes the control bandwidth wider, and at the same time makes a variation of the output voltage very small at sudden changes of resistive load and the input voltage. The 2DOF digital controller whose parameters are determined by the proposed method is actually implemented on a DSP and is connected to a DC-DC converter. Experimental studies demonstrate that this type of digital controller can satisfy given specifications.