• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.29-32
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• 2024

This Paper presents an analog charge-pump based phase-locked loop(PLL) for stabilizing the oscillation frequency of Ring Oscillator type Time-to-Digital Converter(TDC) in discrete Time-of-Flight Light detection and ranging(dToF LiDAR). To ensure the high resolution and accuracy of TDC, PLL is designed by stabilizing the oscillation frequency of TDC and reducing the phase noise. Even though the target time resolution of TDC is 200 ps, both PLL and TDC are designed with an operating frequency of 8.8 GHz due to variations in parasitic components after the process. The locking time of PLL is accomplished to stabilize the system with a fast locking time of PLL. The PLL is realized that locking time is less than 2.4 us, phase noise is -82.57 dBc/Hz at 1 MHz offset and the reference spur of 8.8 GHz is -46.24 dBc.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.137-143
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• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.156-164
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• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.33-40
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• 2024

Recent advancements in computing-in-memory (CIM) have enabled substantial energy efficiency by leveraging charge-domain operations and multi-bit input mechanisms. However, earlier designs still suffer from elevated power consumption and often compromise computation signal-to-noise ratio (SNR) to enhance energy efficiency. In this study, we introduce a CIM processor optimized for energy efficiency and accuracy in multi-bit input/weight-parallel operations, featuring four main innovations: (1) a 10T2C sign-magnitude cell that utilizes voltage-capacitance-ratio (VCR) decoding for 5-bit analog inputs with only two supply voltage levels, (2) a charge reuse technique for the computation word line (CWL) to lower input driver power requirements, (3) a signal-amplifying noise-canceling voltage-to-time converter (SANC-VTC) to boost SNR, and (4) a distribution-aware time-to-digital converter (DA-TDC) aimed at reducing ADC power consumption. The proposed CIM processor, implemented in 28 nm CMOS technology with a 1.25 mm² footprint, achieves a power consumption of 4.44 mW and an energy efficiency of 332 TOPS/W, reaching a benchmark accuracy of 72.43% (tested on ImageNet with ResNet50, 5-bit input/5-bit weight).