• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.629-634
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• 2008

In this paper, we propose a simple numerical formula which can estimate the additional delay time due to interconnection branches in general source-termination scheme. We show that interconnection branches have influence on both signal quality and time delay. Using the proposed numerical formula, time delay can be easily predicted by system designers.

• East Asian mathematical journal
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• v.37 no.1
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• pp.141-147
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• 2021

In [1], we studied the PDE system with time-varing delay. Time delay occurs due to loosening in a high-speed moving axially directed membrane (string, belt, or plate) at production. Our purpose in this work derives a mathematical model with internal time delay. First, we consider the physical phenomenon of axially moving membrane with respect to kinetic energy, potential energy and work done. By the energy conservation law in physics, we get the second order nonlinear PDE system with internal time delay.

• International journal of advanced smart convergence
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• v.5 no.1
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• pp.34-46
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• 2016

Networked Control System (NCS) has evolved in the past decade through the advances in communication technology. The problems involved in NCS are broadly classified into two categories namely network issues due to network and control performance due to system network. The network problems are related to bandwidth allocation, scheduling and network security, and the control problems deal with stability analysis and delay compensation. Various delays with variable length occur due to sharing a common network medium. Though most delays are very less and mostly neglected, the network induced delay is significant. It occurs when sensors, actuators, and controllers exchange data packet across the communication network. Networked induced delay arises from sensor to controller and controller to actuator. This paper presents an adaptive delay compensation process for efficient control. Though Smith predictor has been commonly used as dead time compensators, it is not adaptive to match with the stochastic behavior of network characteristics. Time delay adaptive compensation gives an effective control to solve dead time, and creates a virtual environment using the plant model and computed delay which is used to compensate the effect of delay. This approach is simulated using TrueTime simulator that is a Matlab Simulink based simulator facilitates co-simulation of controller task execution in real-time kernels, network transmissions and continuous plant dynamics for NCS. The simulation result is analyzed, and it is confirmed that this control provides good performance.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.3
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• pp.258-263
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• 2011

In the bilateral tele-operation system, time delay may be a critical problem. Even if system modeling error or time delay occurs, when applied to wave transformation system, the system's stability can be achieved. Using the characteristic b which is an important parameter of wave transformation, the system can display robust performance for time delay. However, since assuming and that the time delay was fixed developing a theory, a stability cannot be guaranteed about the time-varying delay. Therefore, In the paper, Therefore, in this paper, we studied for the method that controls this by applying the fuzzy algorithm which surveyed the timevarying delay characteristics and can adjust the b according to it adaptively.

• Journal of IKEEE
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• v.23 no.3
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• pp.899-903
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• 2019

In networked control systems, time-varying delay of the transmitting signal is inevitable. If the transmission delay is longer than the fixed sampling time, the system will be unstable. To solve this problem, this paper proposes the method to predict the delay using logic-based fuzzy neural networks, and the predicted time delay will be used as a sampling time in the networked control systems. To verify the effectiveness of the proposed method, the delay data collected from the real system are used to train and test the logic-based fuzzy neural networks.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.11
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• pp.741-746
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• 2004

When investigating a control problem for network based control systems, the main issue is network-induced delay. This delay can degrade the performance of control systems designed without considering the delay and even destabilize the system. In this paper, we consider the stabilization of network based control systems, where there is bounded time-varying delay. This delay is treated like parameter variation of a discrete time system. The state feedback controller design is formulated as linear matrix inequality. Finally, we show that the stability of control systems designed with considering the delay is superior to that is not so.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.1-7
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• 2000

This paper studies the delay-characteristics using the singular values and vectors of Hankel operators for input delay systems. First, the computational method of Hankel singular values and their corresponding singular vectors are introduced, and then it is analytically provea that all the Hankel singular vlues have a monotone increasing properties as the length of delay time increases. Furthermore, through a simple numerical example, it is shown that the Hankel singular values are dependent only on the ratio of the time constant of a lumped parameter system to the length of delay , and in case that the time constant is relatively larger than the delay time, the lumped parameter characteristic has a great influence on the input delay systems.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.842-849
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• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.