• Title/Summary/Keyword: Through Silicon Via

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Internal Defect Position Analysis of a Multi-Layer Chip Using Lock-in Infrared Microscopy (위상잠금 적외선 현미경 관찰법을 이용한 다층구조 칩의 내부결함 위치 분석)

  • Kim, Seon-Jin;Lee, Kye-Sung;Hur, Hwan;Lee, Haksun;Bae, Hyun-Cheol;Choi, Kwang-Seong;Kim, Ghiseok;Kim, Geon-Hee
    • Journal of the Korean Society for Nondestructive Testing
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    • v.35 no.3
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    • pp.200-205
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    • 2015
  • An ultra-precise infrared microscope consisting of a high-resolution infrared objective lens and infrared sensors is utilized successfully to obtain location information on the plane and depth of local heat sources causing defects in a semiconductor device. In this study, multi-layer semiconductor chips are analyzed for the positional information of heat sources by using a lock-in infrared microscope. Optimal conditions such as focal position, integration time, current and lock-in frequency for measuring the accurate depth of the heat sources are studied by lock-in thermography. The location indicated by the results of the depth estimate, according to the change in distance between the infrared objective lens and the specimen is analyzed under these optimal conditions.

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

  • Yang, Chung Mo;Kim, Hee Yeoun;Park, Jae Hong
    • Journal of Sensor Science and Technology
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    • v.24 no.1
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    • pp.10-14
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    • 2015
  • This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

Performance-aware Dynamic Thermal Management by Adaptive Vertical Throttling in 3D Network-on-Chip (3D NoC 구조에서 성능을 고려한 어댑티브 수직 스로틀링 기반 동적 열관리 기법)

  • Hwang, Junsun;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.7
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    • pp.103-110
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    • 2014
  • Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

A Study on the Fabrication of p-type poly-Si Thin Film Transistor (TFT) Using Sequential Lateral Solidification(SLS) (SLS 공정을 이용한 p-type poly-Si TFT 제작에 관한 연구)

  • Lee, Yun-Jae;Park, Jeong-Ho;Kim, Dong-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.51 no.6
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    • pp.229-235
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    • 2002
  • This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

Fabrication of Superhydrophobic molecules Nanoarray by Dip-pen Nanolithography (나노리소그라피 기술을 이용한 초소수성 불소 실란 분자의 나노패턴 제조)

  • Yeon, Kyung-Heum;Kang, Pil-Seon;Kim, Kyung-Min;Lim, Jun-Hyurk
    • Journal of Adhesion and Interface
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    • v.19 no.4
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    • pp.163-166
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    • 2018
  • Dip-pen nanolithography(DPN) is an atomic force microscope (AFM) based method of generating nano- or micro-patterns. This technique has been used to transfer various ink materials on the substrate through water meniscus formed between AFM tip and the substrate surface. In this study, the heptadecafluoro-1,1,2,2-tetrahydrodecyltrimethoxysilane (HDFDTMS) ink materials were coated on the pre-coated AFM tip surface with the HDFDTMS molecules. When the tip brought into contact with the hydroxyl-functionalized silicon surface, HDFDTMS ink molecules have been successfully transported from the tip onto the surface via water meniscus. The created array and passivation area showed stable structures on the surface, and the transport of ink materials from the AFM tip to the surface followed linear increase in pattern size with contact time.

Heat Dissipation Trends in Semiconductors and Electronic Packaging (반도체 및 전자패키지의 방열기술 동향)

  • S.H. Moon;K.S. Choi;Y.S. Eom;H.G. Yun;J.H. Joo;G.M. Choi;J.H. Shin
    • Electronics and Telecommunications Trends
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    • v.38 no.6
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    • pp.41-51
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    • 2023
  • Heat dissipation technology for semiconductors and electronic packaging has a substantial impact on performance and lifespan, but efficient heat dissipation is currently facing limited improvement. Owing to the high integration density in electronic packaging, heat dissipation components must become thinner and increase their performance. Therefore, heat dissipation materials are being devised considering conductive heat transfer, carbon-based directional thermal conductivity improvements, functional heat dissipation composite materials with added fillers, and liquid-metal thermal interface materials. Additionally, in heat dissipation structure design, 3D printing-based complex heat dissipation fins, packages that expand the heat dissipation area, chip embedded structures that minimize contact thermal resistance, differential scanning calorimetry structures, and through-silicon-via technologies and their replacement technologies are being actively developed. Regarding dry cooling using single-phase and phase-change heat transfer, technologies for improving the vapor chamber performance and structural diversification are being investigated along with the miniaturization of heat pipes and high-performance capillary wicks. Meanwhile, in wet cooling with high heat flux, technologies for designing and manufacturing miniaturized flow paths, heat dissipating materials within flow paths, increasing heat dissipation area, and reducing pressure drops are being developed. We also analyze the development of direct cooling and immersion cooling technologies, which are gradually expanding to achieve near-junction cooling.

The Development of an Electroconductive SiC-ZrB2 Ceramic Heater through Spark Plasma Sintering

  • Ju, Jin-Young;Kim, Cheol-Ho;Kim, Jae-Jin;Lee, Jung-Hoon;Lee, Hee-Seung;Shin, Yong-Deok
    • Journal of Electrical Engineering and Technology
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    • v.4 no.4
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    • pp.538-545
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    • 2009
  • The SiC-$ZrB_2$ composites were fabricated by combining 30, 35, 40 and 45vol.% of Zirconium Diboride (hereafter, $ZrB_2$) powders with Silicon Carbide (hereafter, SiC) matrix. The SiC-$ZrB_2$ composites, the sintered compacts, were produced through Spark Plasma Sintering (hereafter, SPS), and its physical, electrical, and mechanical properties were examined. Also, the thermal image analysis of the SiC-$ZrB_2$ composites was examined. Reactions between $\beta$-SiC and $ZrB_2$ were not observed via X-Ray Diffractometer (hereafter, XRD) analysis. The relative density of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$, SiC+40vol.%$ZrB_2$, and SiC+45vol.%$ZrB_2$ composites were 88.64%, 76.80%, 79.09% and 88.12%, respectively. The XRD phase analysis of the sintered compacts demonstrated high phase of SiC and $ZrB_2$ but low phase of $ZrO_2$. Among the SiC-$ZrB_2$ composites, the SiC+35vol.%$ZrB_2$ composite had the lowest flexural strength, 148.49MPa, and the SiC+40vol.%$ZrB_2$ composite had the highest flexural strength, 204.85MPa, at room temperature. The electrical resistivities of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$, SiC+40vol.%$ZrB_2$ and SiC+45vol.%$ZrB_2$ composites were $6.74\times10^{-4}$, $4.56\times10^{-3}$, $1.92\times10^{-3}$, and $4.95\times10^{-3}\Omega{\cdot}cm$ at room temperature, respectively. The electrical resistivities of the SiC+30vol.%$ZrB_2$, SiC+35vol.%$ZrB_2$ SiC+40vol.%$ZrB_2$ and SiC+45[vol.%]$ZrB_2$ composites had Positive Temperature Coefficient Resistance (hereafter, PTCR) in the temperature range from $25^{\circ}C$ to $500^{\circ}C$. The V-I characteristics of the SiC+40vol.%$ZrB_2$ composite had a linear shape. Therefore, it is considered that the SiC+40vol.%$ZrB_2$ composite containing the most outstanding mechanical properties, high resistance temperature coefficient and PTCR characteristics among the sintered compacts can be used as an energy friendly ceramic heater or electrode material through SPS.

A Study on Wafer-Level 3D Integration Including Wafer Bonding using Low-k Polymeric Adhesive (저유전체 고분자 접착 물질을 이용한 웨이퍼 본딩을 포함하는 웨이퍼 레벨 3차원 집적회로 구현에 관한 연구)

  • Kwon, Yongchai;Seok, Jongwon;Lu, Jian-Qiang;Cale, Timothy;Gutmann, Ronald
    • Korean Chemical Engineering Research
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    • v.45 no.5
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    • pp.466-472
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    • 2007
  • A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

Synthesis and Characterization of The Electrolessly Deposited Co(Re,P) Film for Cu Capping Layer (무전해 도금법으로 제조된 Co(Re,P) capping layer제조 및 특성 평가)

  • Han, Won-Kyu;Kim, So-Jin;Ju, Jeong-Woon;Cho, Jin-Ki;Kim, Jae-Hong;Yeom, Seung-Jin;Kwak, Noh-Jung;Kim, Jin-Woong;Kang, Sung-Goon
    • Korean Journal of Materials Research
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    • v.19 no.2
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    • pp.61-67
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    • 2009
  • Electrolessly deposited Co (Re,P) was investigated as a possible capping layer for Cu wires. 50 nm Co (Re,P) films were deposited on Cu/Ti-coated silicon wafers which acted as a catalytic seed and an adhesion layer, respectively. To obtain the optimized bath composition, electroless deposition was studied through an electrochemical approach via a linear sweep voltammetry analysis. The results of using this method showed that the best deposition conditions were a $CoSO_4$ concentration of 0.082 mol/l, a solution pH of 9, a $KReO_4$ concentration of 0.0003 mol/l and sodium hypophosphite concentration of 0.1 mol/L at $80^{\circ}C$. The thermal stability of the Co (Re,P) layer as a barrier preventing Cu was evaluated using Auger electron spectroscopy and a Scanning calorimeter. The measurement results showed that Re impurities stabilized the h.c.p. phase up to $550^{\circ}C$ and that the Co (Re,P) film efficiently blocked Cu diffusion under an annealing temperature of $400^{\circ}C$ for 1hr. The good barrier properties that were observed can be explained by the nano-sized grains along with the blocking effect of the impurities at the fast diffusion path of the grain boundaries. The transformation temperature from the amorphous to crystal structure is increased by doping the Re.

Enterococcus faecium LKE12 Cell-Free Extract Accelerates Host Plant Growth via Gibberellin and Indole-3-Acetic Acid Secretion

  • Lee, Ko-Eun;Radhakrishnan, Ramalingam;Kang, Sang-Mo;You, Young-Hyun;Joo, Gil-Jae;Lee, In-Jung;Ko, Jae-Hwan;Kim, Jin-Ho
    • Journal of Microbiology and Biotechnology
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    • v.25 no.9
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    • pp.1467-1475
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    • 2015
  • The use of microbial extracts containing plant hormones is a promising technique to improve crop growth. Little is known about the effect of bacterial cell-free extracts on plant growth promotion. This study, based on phytohormonal analyses, aimed at exploring the potential mechanisms by which Enterococcus faecium LKE12 enhances plant growth in oriental melon. A bacterial strain, LKE12, was isolated from soil, and further identified as E. faecium by 16S rDNA sequencing and phylogenetic analysis. The plant growth-promoting ability of an LKE12 bacterial culture was tested in a gibberellin (GA)-deficient rice dwarf mutant (waito-C) and a normal GA biosynthesis rice cultivar (Hwayongbyeo). E. faecium LKE12 significantly improved the length and biomass of rice shoots in both normal and dwarf cultivars through the secretion of an array of gibberellins (GA1, GA3, GA7, GA8, GA9, GA12, GA19, GA20, GA24, and GA53), as well as indole-3-acetic acid (IAA). To the best of our knowledge, this is the first study indicating that E. faecium can produce GAs. Increases in shoot and root lengths, plant fresh weight, and chlorophyll content promoted by E. faecium LKE12 and its cell-free extract inoculated in oriental melon plants revealed a favorable interaction of E. faecium LKE12 with plants. Higher plant growth rates and nutrient contents of magnesium, calcium, sodium, iron, manganese, silicon, zinc, and nitrogen were found in cell-free extract-treated plants than in control plants. The results of the current study suggest that E. faecium LKE12 promotes plant growth by producing GAs and IAA; interestingly, the exogenous application of its cell-free culture extract can be a potential strategy to accelerate plant growth.