• Journal of the Korea Convergence Society
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• v.8 no.5
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• pp.161-167
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• 2017

We have fabricated and characterized $32{\times}32$ photonic quantum ring (PQR) laser arrays uniformly operable with $0.98{\mu}A$ per ring at room temperature. The typical threshold current, threshold current density, and threshold voltage are 20 mA, $0.068A/cm^2$, and 1.38 V. The top surface emitting PQR array contains GaAs multiquantum well active regions and exhibits uniform characteristics for a chip of $1.65{\times}1.65mm^2$. The peak power wavelength is $858.8{\pm}0.35nm$, the relative intensity is $0.3{\pm}0.2$, and the linewidth is $0.2{\pm}0.07nm$. We also report the wavelength division multiplexing system experiment using angle-dependent blue shift characteristics of this laser array. This photonic quantum ring laser has angle-dependent multiple-wavelength radial emission characteristics over about 10 nm tuning range generated from array devices. The array exhibits a free space detection as far as 6 m with a function of the distance.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.239-245
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• 2013

The data retention characteristics depending on neighbor cell's threshold voltage (Vt) in a multilevel NAND flash memory is studied. It is found that a Vt shift (${\Delta}Vt$) of the noted cell during a thermal retention test is increased as the number of erase-state (lowest Vt state) cells surrounding the noted cell increases. It is because a charge loss from a floating gate is originated from not only intrinsic mechanism but also lateral electric field between the neighboring cells. From the electric field simulation, we can find that the electric field is increased and it results in the increased charge loss as the device is scaled down.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.267.1-267.1
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• 2016

본 연구에서는 nematic 액정의 종류 중 하나인 5CB (4-Cyano-4'-pentylbiphenyl) 물질을 박막 트랜지스터 (TFT)의 passivation 층으로 사용했을 때 그 전기적 특성향상을 확인하였다. RF-magnetron sputtering법으로 증착된 비정질 InGaZnO 박막을 활성층으로 사용한 TFT를 제작하여 그 활성층 위에 drop형식으로 passivation 하였다. 그 결과, drain current (I_DS)가 약 10배 정도 증가하고, linear region(V_D=0.5V)에서 mobility와 subthreshold slope(SS)이 각각 6.7에서 12.2, 0.3에서 0.2로 향상되는 것이 보였다. 이것은 gate bias가 인가되었을 때 freedericksz 전이를 통한 액정의 배향과 이때 형성된 dipole 형성에 의한 것으로 보이며, 이러한 LC의 배향은 편광현미경을 통하여 표면과 수직으로 배향한다는 사실을 확인 할 수 있었고 이 LC-passivation된 a-IGZO TFT의 전기적 특성의 향상에 대한 mechanism을 제시하였다. 그리고 배향한 LC가 가지는 dipole에 의해 bias stress 상황에서 독특한 electron trapping과 recovery의 증폭효과가 나타났다. V_G=+20V의 positive gate bias stress를 1000s동안 가했을 때, passivation되지 않은 a-IGZO TFT의 경우 +4V의 threshold voltage shift(${\Delta}V$_TH)가 발생되었고, 바로 -20V의 negative gate bias를 30s간 가해주었을 때 -2.5V의 ${\Delta}V$_TH가 발생하였다. 반면 LC-passivation된 a-IGZO TFT의 경우 각각 +5V와 -4V의 ${\Delta}V$_TH로 더 큰 변화를 가져왔다. 이러한 LC에 의한 electron trapping/recovery 증폭효과에 대한 model을 제시하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.294.1-294.1
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• 2016

Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.211.1-211.1
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• 2015

최근 용액 공정을 이용한 산화물 반도체에 대한 연구가 활발히 진행되고 있다. 넓은 밴드갭을 가지고 있는 산화물 반도체는 높은 투과율을 가지고 있어 투명 디스플레이에 적용이 가능하다. 기존의 박막 진공증착 방법은 진공상태를 유지하기 위한 장비의 가격이 비싸며, 대면적의 어려움, 높은 생산단가 등으로 생산율이 높지 않다. 하지만 용액 공정을 이용하면 대기압에서 증착이 가능하고 대면적화가 가능하다. 그리고 각각의 조성비를 조절하는 것이 가능하다. 이러한 장점에도 불구하고, 소자의 신뢰성이나 저온공정은 중요한 이슈이다. Instability는 threshold voltage (Vth)의 shift 및 on/off switching의 신뢰성과 관련된 parameter이다. 용액은 소자의 전기적 특성을 열화 시키는 수분 과 탄소계열의 불순물을 다량 포함 하고 있어 고품질의 박막을 형성하기 위해서는 고온의 열처리가 필요하다. 기존의 열처리는 고온에서 장시간 이루어지기 때문에 유리나 플라스틱, 종이 기판의 소자에서는 불가능하지만 $100^{\circ}C$ 이하의 저온 공정인 microwave를 이용하면 유리, 플라스틱, 종이 기판에서도 적용이 가능하다. 본 연구에서는 산화물 반도체 중에서 InGaZnO (IGZO)를 용액 공정으로 제작한 juctionless thin-film transistor를 제작하여 기존의 열처리를 이용하여 처리한 소자와 microwave를 이용해서 열처리한 소자의 전기적 특성을 한 달 동안 관찰 하였다. 또한 In:Zn의 비율을 고정한 후 Ga의 비율을 달리하여 특성을 비교하였다. 먼저 p-type bulk silicon 위에 SiO2 산화막이 100 nm 증착된 기판에 RCA 클리닝을 진행 하였고, solution InGaZnO 용액을 spin coating 방식으로 증착하였다. Coating 후에, solvent와 수분을 제거하기 위해서 $180^{\circ}C$에서 10분 동안 baking공정을 하였다. 이후 furnace열처리와 microwave열처리를 비교하기 위해 post-deposition-annealing (PDA)으로 furnace N2 분위기에서 $600^{\circ}C$에서 30분, microwave를 1800 W로 2분 동안 각각의 샘플에 진행하였다. 또한, HP 4156B semiconductor parameter analyzer를 이용하여 제작된 TFT의 transfer curve를 측정하였다. 그 결과, microwave 열처리한 소자의 경우 기존의 furnace 열처리 소자와 비교하여 높은 mobility, 낮은 hysteresis 값을 나타내었으며, 1달간 소자의 특성을 관찰하였을 때 microwave 열처리한 소자의 경우 전기적 특성이 거의 변하지 않는 것을 확인하였다. 따라서 향후 용액공정, 저온공정을 요구하는 소자 공정에 있어 열처리방법으로 microwave를 이용한 활용이 기대된다.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.328-332
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• 2014

Thin film transistors (TFTs) with an amorphous silicon zinc tin oxide (a-2SZTO) channel layer have been fabricated using an RF magnetron sputtering system. The effect of the change of excitation electron on the variation of the total interfacial trap states of a-2SZTO systems was investigated depending on sputtering power, since the interfacial state could be changed by changing sputtering power. It is well known that Si can effectively reduce the generation of the oxygen vacancies. However, The a-2SZTO systems of ZTO doped with 2 wt% Si could be degraded because the Si peripheral electron belonging to a p-orbital affects the amorphous zinc tin oxide (a-ZTO) TFTs of the s-orbital overlap structure. We fabricated amorphous 2 wt% Si-doped ZnSnO (a-2SZTO) TFTs using an RF magnetron sputtering system. The a-2SZTO TFTs show an improvement of the electrical property with increasing power. The a-2SZTO TFTs fabricated at a power of 30 W showed many of the total interfacial trap states. The a-2SZTO TFTs at a power of 30 W showed poor electrical property. However, at 50 W power, the total interfacial trap states showed improvement. In addition, the improved total interfacial states affected the thermal stress of a-2SZTO TFTs. Therefore, a-2SZTO TFTs fabricated at 50 W power showed a relatively small shift of threshold voltage. Similarly, the activation energy of a-2SZTO TFTs fabricated at 50 W power exhibits a relatively large falling rate (0.0475 eV/V) with a relatively high activation energy, which means that the a-2SZTO TFTs fabricated at 50 W power has a relatively lower trap density than other power cases. As a result, the electrical characteristics of a-2SZTO TFTs fabricated at a sputtering power of 50 W are enhanced. The TFTs fabricated by rf sputter should be carefully optimized to provide better stability for a-2SZTO in terms of the sputtering power, which is closely related to the interfacial trap states.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.47-52
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• 2008

As the packing density of IC devices gets ever higher, the thickness of the gate $SiO_2$ layer of the MOS devices is now required to be reduced down to 1 nm. For such a thin $SiO_2$ layer, the MOS device cannot operate properly because of tunneling current and threshold voltage shift. Hence there has been much effort to develop new dielectric materials which have higher dielectric constants than $SiO_2$ and is free from such undesirable effects. In this work, the physical and electrical characteristics of ALD $ZrO_2$ film have been studied. After deposition of a thin ALD $ZrO_2$ film, it went through thermal treatment in the presence of argon gas at $800^{\circ}C$ for 1 hr. The characteristics of morphology, crystallization kinetics, and interfacial layer of $Pt/ZrO_2/Si$ samples have been investigated by using the analyzing instruments like XRD, TEM and C-V plots. It has been found that the characteristics of the $Pt/ZrO_2/Si$ device was enhanced by the thermal treatment.

• Journal of Information Display
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• v.9 no.4
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• pp.21-29
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• 2008

We studied both the wavelength and intensity dependent photo-responses (photofield-effect) in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs). During the a-IGZO TFT illumination with the wavelength range from $460\sim660$ nm (visible range), the off-state drain current $(I_{DS_off})$ only slightly increased while a large increase was observed for the wavelength below 400 nm. The observed results are consistent with the optical gap of $\sim$3.05eV extracted from the absorption measurement. The a-IGZO TFT properties under monochromatic illumination ($\lambda$=420nm) with different intensity was also investigated and $I_{DS_off}$ was found to increase with the light intensity. Throughout the study, the field-effect mobility $(\mu_{eff})$ is almost unchanged. But due to photo-generated charge trapping, a negative threshold voltage $(V_{th})$ shift is observed. The mathematical analysis of the photofield-effect suggests that a highly efficient UV photocurrent conversion process in TFT off-region takes place. Finally, a-IGZO mid-gap density-of-states (DOS) was extracted and is more than an order of magnitude lower than reported value for hydrogenated amorphous silicon (a-Si:H), which can explain a good switching properties observed for a-IGZO TFTs.