• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.62-62
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• 2011

현재 TFT의 주요 재료로 사용되는 비정질 실리콘은 전하 이동도가 매우 작아 고속 스위칭과 같은 고성능을 구현하기 어려우며 이동도 향상을 위해 고온 공정이 적용되야 하는 단점을 가지고 있다. 이러한 문제를 해결하기 위해 전하 이동도가 큰 박막재료를 바탕으로 박막 트랜지스터의 연구개발이 필요하며 이를 위한 해결책 중 새로운 스위칭 동작원리를 제공하며 고 이동도를 갖는 비정질 칼코지나이드 재료가 각광 받고 있다. 본 연구에서는 박막 스위칭 소자 응용을 위해 GeTe 재료를 기반으로 Se을 치환하여 GeSexTe1-x 박막을 제작한 후 소자의 전기적 특성을 평가하였다. GeTe 박막의 결정화 온도는 $187^{\circ}C$였으며 Se을 점진적으로 첨가한 GeSexTe1-x (X=0.2, 0.4, 0.6) 박막의 경우 각각 $213^{\circ}C$, $240^{\circ}C$, $287^{\circ}C$로 측정되었다. 이는 상대적으로 Ge과 Se의 결합에너지가 Ge과 Te의 결합에너지 보다 크기 때문에 Se 함량의 증가에 따라 비정질상의 안정성이 증가된 것으로 판단된다. 비교적 열적 안정성이 높은 3가지의 각각 다른 Se함량을 가진 Ge1.07 Se0.50 Te0.43, Ge1.07 Se0.68 Te0.26, Ge0.95 Se0.90 Te0.15의 소자를 제작하여 스위칭 특성을 분석하였다. GeTe의 경우 전형적인 메모리 스위칭 특성이 나타난 반면 위의 조성을 갖는 박막의 경우 반복적인 문턱 스위칭 특성을 보였다. 이는 Se이 첨가되면서 열적 안정성의 증가로 인해 스위칭이 일어난 후에도 비정질 상을 유지하기 때문이라 판단된다. 각각 제작된 소자에서 인가 전압의 증가와 펄스의 rising time 감소에 따라 더 빠른 스위칭 시간을 보였으며 Se함량이 감소함에 따라 스위칭 전압 또한 감소하는 것을 확인하였다. On 상태의 저항은 Se 함량에 따라 크게 차이가 없었지만 Off 상태의 저항은 Se 함량이 증가됨에 따라 증가되는 것을 확인하였다. 결과적으로 Se 함량에 따른 스위칭 특성의 최적화를 통해 고성능 스위칭 소자에 적용될 수 있을 것이라 판단된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.469-470
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• 2008

We have studied electro-optic characteristics as a function of splay elastic constants ($K_{11}$) in the fringe-field switching (FFS) mode using the LC with positive dielectric anisotropy. When $K_{11}$ is increased from 7.7pN to 11.7pN, a maximum transmittance is slightly increased and rising time become a little bit fast. However, operating voltage and threshold voltage is independent. In opposition to rising time, decay time is not affected by $K_{11}$. We already know that $K_{11}$ affects tilt angle of liquid crystals. Therefore, on the occasion of high $K_{11}$, liquid crystals are mainly affected by twist deformation because the higher $K_{11}$, the less tilt angle. In the FFS device, high $K_{11}$ is favorable to reduce tilt angle in on state and thus improve rising response time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.24-30
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• 2007

Latching optical switches and optical logic gates with AND or OR, and the INVERT functionality are demonstrated, for the first time, by the monolithic integration of a differential typed vertical cavity laser with depleted optical thyristor (VCL-DOT) structure with a low threshold current of 0.65 mA, a high slope efficiency of 0.38 mW/mA, and high sensitivity to input optical light. Many kinds of logic functions (AND, OR, NAND, NOR, and INVERT) are experimentally demonstrated using a differential switching operation scheme changing the intensity of a reference input beam without any changes of electrical circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1373-1379
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• 2007

A modified adaptive switching median filter for impulse noise removal, which has the noise detection step and the noise filtering step, is proposed in this paper. In the noise detection step, we use the detection threshold which is earned by calculating the intensity differences between pixels nearby with each other in localized window, to determine whether the pixels in the image are noise or not. Then in the noise filtering step, we will only remove the corrupted pixels and remain the good pixels. By the noise detection result, we can easily get the local noise density of the image, and use it to consider the filtering mask size and the times of filtering iteration according to different localized noise corruptions. For Setting the simulation result, we compared the proposed method to conventional median filters with several test images corrupted by various impulse noise densities. We also use the peak signal-to-noise ratio (PSNR) to evaluate restoration performance, the simulation results demonstrate that the proposed method shows better results than other median-based type filters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.221-225
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• 2016

This paper reports a new method to enable the normally-off operation of AlGaN/GaN heterojunction field-effect transistors (HFETs). A capacitor was connected to the gate input node of a normally-on AlGaN/GaN HFET with a Schottky gate where the Schottky gate acted as a clamping diode. The combination of the capacitor and Schottky gate functioned as a clamp circuit to downshift the input signal to enable the normally-off operation. The normally-off operation with a virtual threshold voltage of 5.3 V was successfully demonstrated with excellent dynamic switching characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.9
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• pp.47-52
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• 2020

With the 4th industrial revolution, condition monitoring using machine learning techniques has become popular among researchers. An overload due to complex operations causes several irregularities in MOSFETs. This study investigated the acquired voltage to analyze the overcurrent effects on MOSFETs using a failure mode effect analysis (FMEA). The results indicated that the voltage pattern changes greatly when the current is beyond the threshold value. Several features were extracted from the collected voltage signals that indicate the health state of a switched-mode power supply (SMPS). Then, the data were reduced to a smaller sample space by using a principal component analysis (PCA). A robust machine learning algorithm, the support vector machine (SVM), was used to classify different health states of an SMPS, and the classification results are presented for different parameters. An SVM approach assisted by a PCA algorithm provides a strong fault diagnosis framework for an SMPS.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1697-1708
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• 2017

This paper proposes an algorithm for the differential protection of an Indirect Symmetrical Phase Shift Transformer (ISPST) by considering the different behaviors of the compensated differential current under internal fault and magnetizing inrush conditions. In this algorithm, a criterion function is defined which is based on the difference of amplitude of the wavelet transformation over a specific frequency band. The function has been used for the discrimination between three phase magnetizing inrush and internal fault condition and requires less than a quarter cycle after disturbance. This method is independent of any coefficient or threshold values of wavelet transformation. The merit of this algorithm is demonstrated by the simulation of different faults in series and excitation unit and magnetizing inrush with varying switching conditions on ISPST using PSCAD/EMTDC. Due to unavailability of in-field large interconnected transformers for such a large number of destructive tests, the results are further verified by Real Time Digital Simulator (RSCAD/RTDS). The proposed algorithm has been compared with the conventional harmonic restraint based method that justifies the application of wavelet transform for differential protection of ISPST. The proposed algorithm has also been verified for different rating of ISPSTs and satisfactory results were obtained.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.3
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• pp.222-230
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• 1998

This paper proposes a new gate drive circuit for high power IGBTs which can reduce the harmful effect of reverse recovery current at turn-on and actively suppress the overvoltage across the driven IGBT at turn-off without a snubber circuit. The turn-on scheme decreases the rising rate of the collector current by inereasing the input capacitance at turn-on transient when the gate-emitter voltage goes above threshold voltage. It results in soft transient of the reverse recovery current with no variation in turn-on delay time. The turn-off driving scheme has adaptive feature to the amplitude of collector current, so that the overvoltage can be limited much effectively at the fault collector current. Experimental results under various normal and fault conditions prove the effectiveness of the proposed circuit.