• 한국전기전자재료학회논문지
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• 제17권6호
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• ETRI Journal
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• 제30권2호
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• pp.308-314
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• 2008

In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

• Transactions on Electrical and Electronic Materials
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• 제12권5호
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• pp.197-199
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• 2011

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1288-1291
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• 2007

We investigated the effect of Cr thickness on the electrical properties of triisopropylsilyl pentacene organic thin-film transistor (OTFT) employing suspended source-drain electrode. With Cr thickness of 10 nm, the field-effect mobility, on/off ratio and subthreshold slope were $0.017\;cm^2/Vs$, $8.78\;{\times}\;10^3$ and 10 V/decade, respectively. By increasing the Cr thickness to 100 nm, the fieldeffect mobility was increased to $0.032\;cm^2/Vs$, on/off ratio to $1.12{\times}10^5$ and subthreshold slope to 1 V/decade.

• 대한전기학회논문지
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• 제41권2호
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• pp.163-169
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• 1992

A new analytical expression for the temperature variation characteristics of hydrogenerated amorphous silicon thin film transistors(a-si:H TFT), between 223K and 433K, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled between -5$0^{\circ}C$ and 9$0^{\circ}C$. The model is based on three functions obtained from the experimental data of IS1DT versus VS1GT. Theoretical results confirm the simple form of the model in terms of the device geometry. It was determined that as the temperature increased, the saturated drain current increased and, at a fixed gate voltage, the device saturated at increasingly larger drain voltages while the threshold voltages decreased.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.118-121
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• 1995

Fabrication and a new analytical expression for the capacitance characteristics of hydrogenerated amorphous silicon thin film transistors(a-Si:H TFTs) is presented and experimentally verified. The results show that the experimental capacitance characteristics are easily measeured. Measured transfer and DC output characteristic curves of a-Si:H TFT are similar to those of the standard MOSFET-IC. The capacitances on bias voltages are in good agreement with experimental data. This capacitance characteristics is suitable for incorporation into a circuit simulator and can be used for computer-aided design of a-Si thin film transistor integrated circuits.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.703-706
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• 2006

Zinc oxide nanocrystals are attractive candidates for a solution-processable semiconductor for high performance thin film field effect transistors. We have studied ZnO thin film transistor fabricated by solution process and have improved $V_{th}$ by controlling the ZnO ink additives. Synthesized ZnO nanoparticles of 30nm were dispersed in solvent to make the ZnO ink. ZnO ink was spin coated on silicon wafer and after heat treatment electrodes were patterned.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.257-260
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• 2010

Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.253-256
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• 2010

Different active layer thicknesses for zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric using injector type atomic layer deposition. The properties of the ZnO TFTs were influenced by the active thickness and width-to-length (W/L) ratio of the device. The threshold voltage of ZnO TFTs shifted positively as the active layer thickness decreased, while the subthreshold slope decreased. The W/L ratio of ZnO TFTs also affected the mobility and subthreshold slope. An optimized TFT structure exhibited an on-tooff current ratio of above 106 with solid saturation.

• 전자공학회논문지A
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• 제32A권5호
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.