• Journal of Information Display
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• v.7 no.3
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• pp.1-4
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (a-Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated as the 2.5 um fine pattern formation technique is integrated with high thermal photo-resist (PR) development. In addition, a novel concept of unique a-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um fine-patterning is a considerably significant technology to obtain higher aperture ratio for higher resolution a-Si TFT-LCD panel realization.

• Korean Journal of Materials Research
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• v.11 no.6
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• pp.527-532
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• 2001

Dry etching of copper film using $O_2$ plasma and H(hfac) has been investigated. A one-step process consisting of copper film oxidation with an $O_2$ plasma and the removal of surface copper oxide by the reaction with H(hfac) to form volatile Cu(hfac)$_2$ and $H_2O$ was carried but. The etching rate of Cu in the range from 50 to 700 /min was obtained depending on the substrate temperature, the H(hfac)/O$_2$ flow rate ratio, and the plasma power. The copper film etch rate increased with increasing RF power at the temperatures higher than 215$^{\circ}C$. The optimum H(hfac)/O$_2$ flow rate ratio was 1:1, suggesting that the oxidation process and the reaction with H(hfac) should be in balance. Cu patterning using a Ti mask was performed at a flow rate ratio of 1:1 on 25$0^{\circ}C$\ulcorner and an isotropic etching profile with a taper slope of 30$^{\circ}$was obtained. Cu dry patterning with a tapered angle which is necessary for the advanced high resolution large area thin film transistor liquid-crystal displays was thus successfully obtained from one step process by manipulating the substrate temperature, RF power, and flow rate ratio.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.116-121
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• 2006

Most high-k materials are well known not to be etched easily, Some problems such as low etch rate poor sidewall angle, plasma damage, and process complexity were emerged from the high-density DRAM fabrication. Chemical mechanical polishing (CMP) by a damascene process was proposed to pattern this high-k material was polished with some commercial silica slurry as a function of pH variation. Sufficient removal rate with adequate selectivity to realize the pattern mask of tera-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible. The planarization was also achieved for the subsequent multi-level processes. Our new CMP approach will provide a guideline for effective patterning of high-k material by CMP technique.

• Journal of IKEEE
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• v.25 no.1
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• pp.64-68
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• 2021

We demonstrate an effect of annealing temperature on imprinting process of BiLaO thin film for liquid crystal alignment. BiLaO prepared sol-gel process was deposited by spin coating on a glass substrate, and then transferred to a pre-fabricated aligned pattern which is fabricated on a silicon wafer by laser interference lithography. Thin film was annealed at different temperature of 100, 150, 200, and 250 ℃. From the polarized optical microscopy analysis, the liquid crystal orientation was not uniform at the annealing temperature of 200 ℃ or lower and the uniform liquid crystal alignment characteristics were confirmed at the annealing temperature of 250 ℃. From atomic force microscopy, the pattern was not transferred at a temperature of 200 ℃ or lower. In contrast, the pattern was transferred at 250 ℃. Anisotropy of the thin film was obtained by the alignment pattern transferred at a temperature of 250 ℃, and the liquid crystal molecules could be evenly oriented on the thin film. Therefore, it was confirmed that the liquid crystal alignment process by the imprinting process of the BiLaO oxide film was affected by the annealing temperature.

• Electrical & Electronic Materials
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• v.9 no.1
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• pp.59-66
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• 1996

Polyimides containing cyclobutane ring in main chain is known to be thermally stable and able to be developed in organic solvents after photolysis with 254 nm UV light. This type of polyimides can be used as promising positive photoresist in VLSI fabrication process. In the current VLSI process, photoresist films are formed by spin coating. The film thickness is more than several hundred nano meters. It seems that there is room for improvement of film coating process by introducing Langmuir Blodgett technique. Thereby ultra thin film photoresist can be formed, and higher density of integration in VLSI be achieved. In the present work, depositing procedure of LB films of this polyimide was investigated. LB film thickness was measured by ellipsometry to evaluate deposited film status. Chemical imidization procedure was studied to avoid several problems in thermal imidization. The pattern of submicron dimension has successfully formed on LB film of 8nm thick, which found showing good contrast.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.281-284
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• 2007

Recently, we have developed p-i-n a-Si:H single junction thin film solar cells with RF (13.56MHz) plasma enhanced chemical vapor deposition (PECVD) system, and also successfully fabricated the mini modules ($>300cm^2$), using the laser patterning technique to form an integrated series connection. The efficiency of a mini module was 7.4% ($Area=305cm^2$, Isc=0.25A, Voc=14.74V, FF=62%). To fabricate large area modules, it is important to optimise the integrated series connection, without damaging the cell. We have newly installed the laser patterning equipment that consists of two different lasers, $SHG-YVO_4$ (${\lambda}=0.532{\mu}m$) and YAG (${\lambda}=1.064{\mu}m$). The mini-modules are formed through several scribed lines such as pattern-l (front TCO), pattern-2 (PV layers) and pattern-3 (BR/back contact). However, in the case of pattern-3, a high-energy part of laser shot damaged the textured surface of the front TCO, so that the resistance between the each cells decreases due to an incomplete isolation. In this study, the re-deposition of SnOx from the front TCO, Zn (BR layer) and Al (back contact) on the sidewalls of pattern-3 scribed lines was observed. Moreover, re-crystallization of a-Si:H layers due to thermal damage by laser patterning was evaluated. These cause an increase of a leakage current, result in a low efficiency of module. To optimize a-Si:H single junction thin film modules, a laser beam profile was changed, and its effect on isolation of scribed lines is discussed in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.68-69
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• 2005

BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.808-810
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• 2005

Inexpensive large area arrays of thin film transistors (TFTs) on flexible substrates will enable many new display products that cannot be cost effectively manufactured by conventional means. This paper presents a new approach for low cost manufacturing of electronic devices using roll-to-roll (R2R) processes exclusively. It was developed in partnership by Hewlett Packard Laboratories and Iowa Thin Film Technologies (ITFT), a solar cell manufacturer. The approach combines ITFT's unique processes for vacuum deposition and etching of semiconductors, dielectrics and metals on continuous plastic webs with a method HP has invented for the patterning and aligning the multiple layers of a TFT with sub-micron accuracy and feature size.

• Journal of the Korean Ceramic Society
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• v.41 no.1
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• pp.13-18
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• 2004

$La_{0.5}Sr_{0.5}CoO_3$ (LSCO) electrodes were prepared on ferroelectric $Sr_{0.9}Bi_{2.1}Ta_2O_9$(SBT) thin films by spin coating method using photosensitive sol-gel solution. Self-patterning technique of photosensitive sol-gel solution has advantages such as simple manufacturing process compared to photoresist/dry etching process. Lanthanum(III) 2-methoxyethoxide, Stronitium diethoxide. Cobalu(II)2-methoxyethoxide were used as starting materials for LSCO electrode. UV irradiation on LSCO thin films lead to decrease solubility by M-O-M bond formation and the solubility difference allows us to obtain self-patternine. There was little composition change of the LSCO thin films between before leaching and after leaching in 2-methoxyethanol. The lowest resistivity of LSCO thin films deposited on $SiO_2$/Si substrate was $1.1{\times}10^{-2}{\Omega}cm$ when the thin film was ennealed at $740^{\circ}C$. The values of Pr/Ps and 2Pr of LSCO/SBT/Pt capacitor on the applied voltage of 5V were 0.51, 8.89 ${\mu}C/cm^2$, respectively.