• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.39-42
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• 2002

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity(WIWNU) were measured as a function of different slurry composition. As a experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows In the first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saving of high costs of slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.759-764
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• 2003

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt％ contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

• Journal of the Korean Electrochemical Society
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• v.2 no.4
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• pp.237-241
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• 1999

The characteristics of copper thin films and via hole filling capability were investigated by pulsed electrodeposition method. Especially, the effects of additives on the properties of copper thin films were studied. Copper films, which were deposited by pulsed electrodeposition using commercial additives, had low tensile stress value under 83.4 MPa and high preferred Cu (111) texture. Via holes with $0.25{\mu}m$ in diameter and 6 : 1 aspect ratio were successfully filled without any defects by superfilling. It was observed that copper microstructure deformed by twining. After heat treatment at $500^{\circ}C$ for 1 k in vacuum furnace, grain size was 1 or 2 times as large as film thickness and the bamboo structure was formed. Heat treated copper films showed good resistivities of $1.8\~2.0{\mu}{\Omega}{\cdot}cm$.

• Proceedings of the Korean Vacuum Society Conference
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• 1995.02a
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• pp.057-58
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• 1995

극소전자 디바이스의 고집적화에 의해 박막배선의 선폭은 0.5$mu extrm{m}$ 이하로 축소되고 있고 상대적으로 높은 전류밀도가 흐르게 된다. 높은 전류밀도하에서는 현재 일반적으로 사용되고 있는 Al을 기본으로 하는 박막배선에서의 electromigration에 의한 결함 발생 그리고 비교적 낮은 전기전도도가 심각한 문제점으로 제기된다. 본 연구에서는 Al과 고전기전도도 물질인 Ag, Cu, 그리고 Au 박막배선에 대해 electromigration에 대한 저항성, 즉 activation energy를 측정 비교함으로써 차세대 극소전자 디바이스를 위한 박막배선재료로서의 가능성을 알아보고자 한다. Electromigration test 및 activation energy를 구하기 위해 순수 Ag, Cu, Al, Au 박막배선을 0.05$\mu\textrm{m}$ 두께, 100$\mu\textrm{m}$ 선폭, 그리고 5000$\mu\textrm{m}$ 길이로 SiO2 열산화막 처리된 pp-Si(100) 기판 위에 진공 증착시켰다. 가속화 실험을 위해 인가된 d.c. 전류밀도는 2$\times$106A/$ extrm{cm}^2$ 이었고, Al과 Au에서는 6$\times$106A/$\textrm{cm}^2$이었다. 실온에서 24$0^{\circ}C$까지의 온도범위에서 d.c.인가후의 저항변화를 측정하여 Median-Time-to-Failure(MTF)를 구한 후 Black 방정식을 이용하여 activation energy를 측정하였다. Activation energy는 Cu가 1.34eV로서 가장 높게 나타났고 Au가 1.01eV, Al이 0.66eV, Ag가 0.29eV의 순으로 측정되었다. 따라서 Cu와 Au 박막배선의 경우 Al보다 electromigration에 대한 저항력이 강한 고활성화에너지 특성을 갖는 고전기전도도 재료로서 차세대 극소전자 디바이스를 위한 대체 박막배선재료로서의 가능성을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.12
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• pp.1353-1361
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• 1992

Holographic optical element(HOE) is fabricated with the properties of lightweight, thin thickness and interconnectivity for free space. Particularly, HOE for optical interconnection and multiple image processing should have a high efficiency and equal spot intensity, Nonlinear equations for 2-dimensional binary phase grating(BPG) structure is solved by computer simulation based on modified Newton method. Computer-generated pattern drawn by plotter is scaled down and translated into the microfilm. After contact printing between the microfilm and silver halide hologram film, phase diffraction grating produces the $5{\times}5$ multiple spots. Experimental results are shown that bleached phase grating has a high efficiency and equal focused beams except central zero order.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.518-522
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• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• Korean Journal of Optics and Photonics
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• v.23 no.1
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• pp.12-16
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• 2012

In the paper, we fabricated a Ni master with $45^{\circ}$-mirror structures for flexible waveguide fabrication. The flexible waveguide films with embedded $45^{\circ}$-angled mirrors at the waveguide ends were successfully fabricated using a UV-imprint process. Next, in order to enhance the reflectivity of the mirrors, Ni(3 nm)-Au(200 nm) bilayers were evaporated on the $45^{\circ}$-angled facets through a locally opened thin mask using an electron beam evaporator. We measured propagation loss, bending loss, mirror loss and bending reliability of the fabricated waveguide.

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.61-66
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• 2018

This research scrutinizes the self-annealing characteristics of copper used to metal interconnection for application of DRAM fabrication process. As the time goes after the copper deposited, the grain of copper is growing. It is called self-annealing. We use the electroplating method for copper deposition and estimate two kinds of electroplating chemicals having different organic additives. As the time of self-annealing is elapsed, sheet resistance decreases with logarithmic dependence of time and is finally saturated. The improvement of sheet resistance is approximately 20%. The saturation time of experimental sample is shorter than that of reference sample. We can find that self-annealing is highly efficient in grain growth of copper through the measurement of TEM analysis. The structure of copper grain is similar to the bamboo type useful for current flow. The results of thermal excursion characteristics show that the reliability of self-annealed sample is better than that of sample annealed at higher temperature. The self-annealed sample is not contained in hillock. The self-annealed samples grow until $2{\mu}m$ and develop in [100] direction more favorable for reliability.