• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.194.1-194.1
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• 2015

Transition metal dichalcogenide (TMD) with layered structure, has recently been considered as promising candidate for next-generation flexible electronic and optoelectronic devices because of its superior electrical, optical, and mechanical properties.[1] Scalability of thickness down to a monolayer and van der Waals expitaxial structure without surface dangling bonds (consequently, native oxides) make TMD-based thin film transistors (TFTs) that are immune to the short channel effect (SCE) and provide very high field effect mobility (${\sim}200cm^2/V-sec$ that is comparable to the universal mobility of Si), respectively.[2] In addition, an excellent photo-detector with a wide spectral range from ultraviolet (UV) to close infrared (IR) is achievable with using $WSe_2$, since its energy bandgap varies between 1.2 eV (bulk) and 1.8 eV (monolayer), depending on layer thickness.[3] However, one of the critical issues that hinders the successful integration of $WSe_2$ electronic and optoelectronic devices is the lack of a reliable and controllable doping method. Such a component is essential for inducing a shift in the Fermi level, which subsequently enables wide modulations of its electrical and optical properties. In this work, we demonstrate n-doping method for $WSe_2$ on poly-4-vinylphenol and poly (melamine-co-formaldehyde) (PVP/PMF) insulating layer and adjust the doping level of $WSe_2$ by controlling concentration of PMF in the PVP/PMF layer. We investigated the doping of $WSe_2$ by PVP/PMF layer in terms of electronic and optoelectronic devices using Raman spectroscopy, electrical measurements, and optical measurements.

• 전자공학회논문지 IE
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• v.43 no.1
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• pp.1-4
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• 2006

The characteristics of polymeric thin-film transistors(TFTs) can be controlled by chemically modifying the surface of the gate dielectric prior to the organic semiconductor. The chemical treatment consists of derivative the tantalum pentoxide($Ta_2O_5$) surface with organic materials to form self-assembled monolayer(SAM). The deposition of an octadecyl-trichlorosilane(OTS), hexamethy-ldisilazone(HMDS), aminopropyltreithoxysilane(ATS) SAM leads to a mobility of $0.01\sim0.06cm2/V{\cdot}s$ in a poly-3-hexylthiophene(P3HT) conjugated polymer. The mobility enhancement mechanism is likely to involve molecular interactions between the polymer and SAM. These result can be used for polymer TFT's dielectric material.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.3
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• pp.279-284
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• 2014

This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by ${\pm}0.25V$ and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by ${\pm}0.50V$. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.418-419
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• 2013

현재, 인듐 주석 산화물(indium tin oxide, ITO) 박막은 가시영역에서 전기적 특성 및 광학적 특성이 우수하기 때문에 평면 디스플레이(flat displays), 박막 트랜지스터(thin film transistors), 태양전지(solar cells) 등을 포함한 광소자에 투명전도성산화물(transparent conducting oxide, TCO) 전극으로 가장 일반적으로 사용되고 있다. 하지만, 이 물질은 밴드갭이 3.4 eV로 다소 작아 다양한 분야의 의료기기, 환경 보호에 응용 가능한 자외선 영역에서 상당히 많은 양의 광흡수가 발생하는 치명적인 문제점을 가지고 있다. 또한, 인듐(Indium)의 급속한 소비는 인듐의 매장량의 한계로 인해 가격을 상승시키는 주요한 원인으로 작용하고 있다. 한편, InGaN 기반의 자외선 발광다이오드 분야에서는 팔라듐(Pd) 기반의 반투명 전극과 은(Ag) 기반의 반사전극을 주로 사용하고 있지만, 낮은 투과도와 낮은 굴절률을 때문에 여전히 자외선 발광다이오드의 광추출 효율(extraction efficiency)에 문제점을 가지고 있다. 따라서 자외선 발광다이오드의 외부양자 효율(external quantum efficiency, EQE)을 높이기 위해 높은 투과도와 GaN와 유사한 굴절률을 가지는 p-형 오믹 전극을 개발해야 한다. 본 연구에서는 초박막의 ITO (16 nm)/Ag (7 nm)/ITO (16 nm) 다층 구조를 갖는 투명전도성 전극을 제작한 후, 열처리 온도에 따른 전기, 광학적 특성에 향상에 대해서 조사하였다. 사용된 산화물/금속/산화물 전극의 구조는 유기발광 다이오드(organic light emitting diode, OLED), 태양전지 등에 많이 사용되는 안정적인 투명 전극을 자외선 LED 소자에 처음 적용하여, ITO의 전체 사용량은 줄이고, ITO 사이에 금속을 삽임함으로써 금속에 의한 전기적 특성 향상과 플라즈몬 효과에 의한 투과도를 높일 수 있는 장점을 가지고 있다. 실험 결과로는, $400^{\circ}C$에서 열처리한 ITO/Ag/ITO 다층 구조는 365 nm에서 84%의 광학적 특성과 9.644 omh/sq의 전기적 특성을 확인하였다. 실험 결과로부터 좀 더 최적화를 수행하면, ITO/Ag/ITO 다층 구조는 자외선 발광다이오드의 투명전도성 전극으로 사용될 수 있을 것이라 기대된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.221-221
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• 2013

Striving to replace the well known silicon nanocrystals embedded in oxides with solution-processable charge-trapping materials has been debated because of large scale and cost effective demands. Herein, a silicon quantum dot-polystyrene nanocomposite (SiQD-PS NC) was synthesized by postfunctionalization of hydrogen-terminated silicon quantum dots (H-SiQDs) with styrene using a thermally induced surface-initiated polymerization approach. The NC contains two miscible components: PS and SiQD@PS, which respectively are polystyrene and polystyrene chains-capped SiQDs. Spin-coated films of the nanocomposite on various substrate were thermally annealed at different temperatures and subsequently used to construct metal-insulator-semiconductor (MIS) devices and thin film field effect transistors (TFTs) having a structure p-$S^{++}$/$SiO_2$/NC/pentacene/Au source-drain. C-V curves obtained from the MIS devices exhibit a well-defined counterclockwise hysteresis with negative fat band shifts, which was stable over a wide range of curing temperature ($50{\sim}250^{\circ}C$. The positive charge trapping capability of the NC originates from the spherical potential well structure of the SiQD@PS component while the strong chemical bonding between SiQDs and polystyrene chains accounts for the thermal stability of the charge trapping property. The transfer curve of the transistor was controllably shifted to the negative direction by chaining applied gate voltage. Thereby, this newly synthesized and solution processable SiQD-PS nanocomposite is applicable as charge trapping materials for TFT based memory devices.

• Korean Journal of Materials Research
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• v.16 no.5
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• pp.302-307
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• 2006

The formation and processing of organic insulators on the device performance have been studied in the fabrication of organic thin film transistors (OTFTs). The series of polyvinyls, poly-4-vinyl phenol(PVP) and polyvinyltoluene (PVT), were used as solutes and propylene glycol monomethyl ether acetate(PGMEA) as a solvent in the formation of organic insulators. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compound. The electrical characteristics measured in the metal-insulator-metal (MIM) structures showed that insulating properties of PVP layers were generally superior to those of PVT layers. Among the layers of PVP series: PVP(10 wt%) copolymer, 5 wt% cross-linked PVP(10 wt%), PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%), the 10 wt% cross-linked PVP(20 wt%) layer showed the lowest leakage current characteristics. Finally, inverted staggered OTFTs using the PVP(20 wt%) copolymer, 5 wt% cross-linked PVP(20 wt%) and 10 wt% cross-linked PVP(20 wt%) as gate insulators were fabricated on the polyether sulphone (PES) substrates. In our experiments, we could obtain the maximum field effect mobility of 0.31 $cm^2/Vs$ in the device from 5 wt% cross-linked PVP(20 wt%) and the highest on/off current ratio of $1.92{\times}10^5$ in the device from 10 wt% cross-linked PVP(20 wt%).

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.2
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• pp.207-212
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• 2013

A novel pixel circuit that uses only n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS-TFTs) to compensate the threshold voltage variation of a OLED driving TFT is proposed. The proposed 6T1C pixel circuit consists of 5 switching TFTs, 1 OLED driving TFT and 1 capacitor. When the threshold voltage of driving TFT varies by ${\pm}0.33$ V, Smartspice simulation results show that the maximum error rate of OLED current is 7.05 % and the error rate of anode voltage of OLED is 0.07 % at Vdata = 5.75 V. Thus, the proposed 6T1C pixel circuit can realize uniform output current with high immunity to the threshold voltage variation of poly-Si TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.761-767
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• 1999

Poly-Si TFTs(polycrystalline silicon thin film transistors) fabricated on a low cost glass substrate have attracted a considerable amount of attention for pixel elements and peripheral driving circuits in AMLCS(active matrix liquid crystal display). In order to apply poly-Si TFTs for high resolution AMLCD, a high operating frequency and reliable circuit performances are desired. A new poly-Si TFT with CLBT(counter doped lateral body terminal) is proposed and fabricated to suppress kink effects and to improve the device stability. And this proposed device with BC(buried channel) is fabricated to increase ON-current and operating frequency. Although the troublesome LDD structure is not used in the proposed device, a low OFF-current is successfully obtained by removing the minority carrier through the CLBT. We have measured the dynamic properties of the poly-Si TFT device and its circuit. The reliability of the TFTs and their circuits after AC stress are also discussed in our paper. Our experimental results show that the BC enables the device to have high mobility and switching frequency (33MHz at $V_{DD}$ = 15 V). The minority carrier elimination of the CLBT suppresses kink effects and makes for superb dynamic reliability of the CMOS circuit. We have analyzed the mechanism in order to see why the ring oscillators do not operate by analyzing AC stressed device characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.