• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.663-665
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• 2000

We fabricated resistive superconducting fault current limiters (SFCL) based on YBCO thin films grown on 2-inch diameter saphire substrates Two SFCLs with nearly identical properties were connected in series to investigate the simultaneous quench. There was a slight difference in the rate of voltage increase between two SFCL units when they were operated independently. This difference. however, resulted in significantly unbalanced power dissipation between the units. This imbalance was removed by connecting a shunt resistor to an SFCL in parallel. The appropriate values of the shunt resistances were $80{\Omega}$ at $75 V_{rms}$. $100{\Omega}$ at $100 V_{rms}$ and $110{\Omega}$ at $120 V_{rms}$, respectively. Increased power input at high voltages also reduced the initial imbalance in power dissipation. but with increase in film temperature to higher than 200 K.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.64-65
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• 2005

The structural and electrical properties of the films are investigated as a function of nitrogen/argon ratio at room temperature and at various deposition temperatures. The phase changes as $Ta_2N$ or TaN in the films were observed as nitrogen/argon ratio increases from 3% to 25%. The phase changes were associated with a change in the resistivity and TCR (temperature coefficient of resistance) of the films. TCR values of the films deposited at room temperature and different nitrogen contents were negative, and strongly decreased with the increase in nitrogen/argon ratio. The Ta2N films deposited at nitrogen/argon ratio of 3% show improved TCR values and thermal stability with increasing deposition temperature. The $Ta_2N$ films grown at nitrogen/argon ratio of 3% and the temperature of $200^{\circ}C$ showed a TCR value of -47 $ppm/^{\circ}C$, which is close to near-zero TCR in the range of deposition temperature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Korean Vacuum Society
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• v.8 no.1
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• pp.75-82
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• 1999

Ion energy is one of the crucial property in thin film deposition by internal ICP assisted I-PVD. As ion energy is determined by the difference between the plasma potential and the substrate bias potential, ICP excitation frequency was tested with medium frequency of 4 MHz and two types of tuning circuits, alternate and floating LC network with a biasing resistor, were tested. The results showed that plasma potential was less than 5 V in a range of Ar pressures, 5mTorr to 30 mTorr, at 4 MHz RF 600 W and 60 V of maximum RF antenna voltage was maintained either at RF input or output terminal. By proper control of RLC circuit installed after after RF antenna, 50V of RF induced voltage on RF antenna was obtained at 500W input power. The total impedance of RF antenna and plasma was around 10$\Omega$, and minimum RF voltage was obtained with a condition of lowest reactance at most 0.05$\Omega$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.6
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• pp.297-301
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• 2006

In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

• Journal of Sensor Science and Technology
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• v.33 no.1
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• pp.56-61
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• 2024

The quality of the display can be managed by effectively managing the temperature generated by the panel during use. Conventional display panels rely on an external reference resistor for temperature monitoring. However, this approach is easily affected by external factors such as temperature variations from the driving circuit and chips. These variations reduce reliability, causing complicated mounting owing to the external chip, and cannot monitor the individual pixel temperatures. However, this issue can be simply and efficiently addressed by integrating temperature sensors during the display panel manufacturing process. In this study, we fabricated and analyzed a temperature sensor integrated into an a-IGZO (amorphous indium-gallium-zinc-oxide) TFT array that was to precisely monitor temperature and prevent the deterioration of OLED display pixels. The temperature sensor was positioned on top of the oxide TFT. Simultaneously, it worked as a light shield layer, contributing to the reliability of the oxide. The characteristics of the array with integrated temperature sensors were measured and analyzed while adjusting the temperature in real-time. By integrating a temperature sensor into the TFT array, monitoring the temperature of the display became easier and more accurate. This study could contribute to managing the lifetime of the display.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.3
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• pp.323-327
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• 2024

The low-temperature coefficient of resistance (TCR) is a crucial factor in the development of space-grade resistors for temperature stability. Consequently, extensive research is underway to achieve zero TCR. In this study, resistors were deposited by co-sputtering nickel-chromium-based composite compositions, metals showing positive TCR, with SiO₂, introducing negative TCR components. It was observed that achieving zero TCR is feasible by adjusting the proportion of negative TCR components in the deposited thin film resistors within certain compositions. Additionally, the correlation between TCR and deposition conditions, such as sputtering power, Ar pressure, and surface roughness, was investigated. We anticipate that these findings will contribute to the study of resistors with very low TCR, thereby enhancing the reliability of space-level resistors operating under high temperatures.

• Journal of Sensor Science and Technology
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• v.7 no.3
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• pp.171-178
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• 1998

Silicon piezoresistive absolute pressure sensor for gas leakage alarm system was developed. This sensor must operate normally in the range of $0{\sim}600\;mmH_{2}O$ pressure, and $0{\sim}100^{\circ}C$ temperature. To make the most of this sensor for gas leakage alarm system, gas must not leak from the sensor itself when the diaphragm of the sensor fractures. Thus, the sealed diaphragm cavity was anodically bonded to pyrex 7740 glass under the condition of $10^{-4}$ torr, at $400^{\circ}C$. The sensitivity of developed sensor was $4.06{\mu}V/VmmH_{2}O$ for $600\;mmH_{2}O$ full-scale pressure range. And temperature compensation method of this sensor is to change bridge-in put-voltage linearly in proportion to the temperature variation by using diode(PXIN4001) or Al thin film resistor. By these methods the temperature effect in the range of $0{\sim}100^{\circ}C$ was compensated over 80 % for offset drift, 95 % for sensitivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.