• 제목/요약/키워드: Thermal insulating substrate

검색결과 47건 처리시간 0.032초

전기화학 공정을 이용한 질화규소 기판 상의 금속 전극 형성에 관한 연구 (Formation of Metal Electrode on Si3N4 Substrate by Electrochemical Technique)

  • 신성철;김지원;권세훈;임재홍
    • 한국표면공학회지
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    • 제49권6호
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    • pp.530-538
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    • 2016
  • There is a close relationship between the performance and the heat generation of the electronic device. Heat generation causes a significant degradation of the durability and/or efficiency of the device. It is necessary to have an effective method to release the generated heat. Based on demands of the printed circuit board (PCB) manufacturing, it is necessary to develop a robust and reliable plating technique for substrates with high thermal conductivity, such as alumina ($Al_2O_3$), aluminium nitride (AlN), and silicon nitride ($Si_3N_4$). In this study, the plating of metal layers on an insulating silicon nitride ($Si_3N_4$) ceramic substrate was developed. We formed a Pd-$TiO_2$ adhesion layer and used APTES(3-Aminopropyltriethoxysilane) to form OH groups on the surface and adhere the metal layer on the insulating $Si_3N_4$ substrate. We used an electroless Ni plating without sensitization/activation process, as Pd particles were nucleated on the $TiO_2$ layer. The electrical resistivity of Ni and Cu layers is $7.27{\times}10^{-5}$ and $1.32{\times}10^{-6}ohm-cm$ by 4 point prober, respectively. The adhesion strength is 2.506 N by scratch test.

온도 민감 형광을 이용한 마이크로 스케일 표면온도 측정 (Surface Temperature Measurement in Microscale with Temperature Sensitive Fluorescence)

  • 정운섭;김성욱;김호영;유정열
    • 대한기계학회논문집B
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    • 제30권2호
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    • pp.153-160
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    • 2006
  • A technique for measuring surface temperature field in micro scale is newly proposed, which uses temperature-sensitive fluorescent (TSF) dye coated on the surface and is easily implemented with a fluorescence microscope and a CCD camera. The TSF dye is chosen among mixtures of various chemical compositions including rhodamine B as the fluorescent dye to be most sensitive to temperature change. In order to examine the effectiveness of this temperature measurement technique, numerical analysis and experiment on transient conduction heat transfer for two different substrate materials, i. e., silicon and glass, are performed. In the experiment, to accurately measure the temperature with high resolution temperature calibration curves were obtained with very fine spatial units. The experimental results agree qualitatively well with the numerical data in the silicon and glass substrate cases so that the present temperature measurement method proves to be quite reliable. In addition, it is noteworthy that the glass substrate is more appropriate to be used as thermally-insulating locally-heating heater in micro thermal devices. This fact is identified in the temperature measuring experiment on the locally-heating heaters made on the wafer of silicon and glass substrates. Accordingly, this technique is capable of accurate and non-intrusive high-resolution measurement of temperature field in microscale.

$SiO_2$와 Co/Ti 이중층 구조의 상호반응 (Interaction of Co/Ti Bilayer with $SiO_2$ Substrate)

  • 권영재;이종무;배대록;강호규
    • 한국진공학회지
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    • 제7권3호
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    • pp.208-213
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    • 1998
  • 최근 셀리사이드(salicide) 제조시 $COSiO_2$의 에피텍셜 성장을 돕기 위하여 Ti층을 삽 입한 Co/Ti/Si 이중층 구조의 실리사이드화가 관심을 끌고 있다. Co/Ti 이중층을 이용한 salicide 트랜지스터가 성공적으로 만들어지기 위해서는 gate 주위의 spacer oxide위에 증착 된 Co/Ti 이중층을 급속열처리할 때 Co/Ti와 $SiO_2$간의 계면에서의 상호반응에 대하여 조사 하였다. Co/Ti 이중층은 $600^{\circ}C$에서 열처리한 후 면저항이 급격하게 증가하기 시작하였는데, 이것은 Co층이 $SiO_2$와의 계면에너지를 줄이기 위하여 응집되기 때문이다. 이때 Co/Ti의 열 처리후 Ti에 의하여 $SiO_2$기판의 일부가 분해됨으로써 절연체의 Ti산화물이 형성되었으나, 이외의 도전성 반응부산물은 발견되지 않았다.

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알루미늄 판상에 글라스 세라믹 후막이 코팅된 절연금속기판의 제조 및 절연특성 (Fabrication and Electrical Insulation Property of Thick Film Glass Ceramic Layers on Aluminum Plate for Insulated Metal Substrate)

  • 이성환;김효태
    • 마이크로전자및패키징학회지
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    • 제24권4호
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    • pp.39-46
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    • 2017
  • 본 연구는 평판형 히터용 금속방열판상의 세라믹 절연층 제조, 즉 절연성 금속기판에 관한 것이다. 반도체나 디스플레이의 열처리 공정 등에 사용되는 평판형 히터를 제조함에 있어서, 온도 균일도를 높이기 위해 금속 방열판으로서 열전도율이 높고, 비교적 가벼우며, 가공성 좋은 알루미늄 합금 기판이 선호된다. 이 알루미늄 기판에 발열 회로 패턴을 형성하기 위해서는 금속 기판에 절연층으로서 고온 안정성이 우수한 세라믹 유전체막을 코팅하여야 한다. 금속 기판상에 세라믹 절연층을 형성함에 있어서 가장 빈번히 발생하는 첫 번째 문제는 금속과 세라믹의 이종재료 간의 큰 열팽창계수 차이와 약한 결합력에 의한 층간박리 및 균열발생이다. 두 번째 문제는 절연층의 소재 및 구조적 결함에 따른 절연파괴이다. 본 연구에서는 이러한 문제점 해소를 위해 금속소재 기판과 세라믹 절연층 사이에 완충층을 도입하여 이들 간의 기계적 매칭과 접합력 개선을 도모하였고, 다중코팅 방법을 적용하여 절연막의 품질과 내전압 특성을 개선하고자 하였다.

$Al_2O_3$ 절연막을 게이트 절연막으로 이용한 공핍형 n-채널 GaAs MOSFET의 제조 (Fabrication of a Depletion mode n-channel GaAs MOSFET using $Al_2O_3$ as a gate insulator)

  • 전본근;이석헌;이정희;이용현
    • 대한전자공학회논문지SD
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    • 제37권1호
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    • pp.1-7
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    • 2000
  • 본 논문에서는 반절연성 GaAs 기판위에 $Al_2O_3$ 절연막이 제이트 절연막으로 이용된 공핍형보드 n형 채널 GaAs MOSFET(depletion mode n-channel GaAs MOSFET)를 제조하였다. 반절연성 GaAs 기판위에 1 ${\mu}$m의 GaAs 버퍼층, 1500 ${\AA}$의 n형 GaAs층, 500 ${\AA}$의 AlAs층, 그리고 50 ${\AA}$의 캡층을 차례로 성장시키고 습식열산화 시켰으며, 이를 통하여 AlAs층은 완전히 $Al_2O_3$층으로 변환되었다. 제조된 MOSFET의 I-V, $g_m$, breakdown특성 측정 등을 통하여 AlAs/GaAs epilayer/S${\cdot}$I GaAs 구조의 습식열산화는 공핍형 모드 GaAs MOSFET를 구현하기에 적합함을 알 수 있다.

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Thermal imprint를 이용한 고밀도 line패턴 형성방법 (High density line patterns fabricated by thermal imprint)

  • 이상문;곽정복;이환수
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.270-270
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    • 2008
  • We present details of experimental results in the fabrication of high density line patterns, using imprint technique that can provide a simple and comparatively cost-effective manufacturing means. Barrier array structures for display or interconnects for semiconductor applications were the aims of this study. For pattern fabrication, a polymer layer (Ajinomoto GX-13 dielectric film) with a thickness of 38um that can act as either an insulating or a dielectric layer was laminated on a substrate. Fine tracks were then formed using a patterned stamp under isostatic pressure. The line width was ranged between 10 to 60 mm. A self-assembled monolayer (SAM) of fluorinated alkylchlorosilane [$CF_3(CF_2)5(CH_2)2SiCl_3$] as an anti-sticking layer was coated on the surface of the stamp prior to thermal imprint to improve the de-molding characteristic.

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Rapid Thermal Annealing at the Temperature of 650℃ Ag Films on SiO2 Deposited STS Substrates

  • Kim, Moojin;Kim, Kyoung-Bo
    • Applied Science and Convergence Technology
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    • 제26권6호
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    • pp.208-213
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    • 2017
  • Flexible opto-electronic devices are developed on the insulating layer deposited stainless steel (STS) substrates. The silicon dioxide ($SiO_2$) material as the diffusion barrier of Fe and Cr atoms in addition to the electrical insulation between the electronic device and STS is processed using the plasma enhanced chemical vapor deposition method. Noble silver (Ag) films of approximately 100 nm thickness have been formed on $SiO_2$ deposited STS substrates by E-beam evaporation technique. The films then were annealed at $650^{\circ}C$ for 20 min using the rapid thermal annealing (RTA) technique. It was investigated the variation of the surface morphology due to the interaction between Ag films and $SiO_2$ layers after the RTA treatment. The results showed the movement of Si atoms in silver film from $SiO_2$. In addition, the structural investigation of Ag annealed at $650^{\circ}C$ indicated that the Ag film has the material property of p-type semiconductor and the bandgap of approximately 1 eV. Also, the films annealed at $650^{\circ}C$ showed reflection with sinusoidal oscillations due to optical interference of multiple reflections originated from films and substrate surfaces. Such changes can be attributed to both formation of $SiO_2$ on Ag film surface and agglomeration of silver film between particles due to annealing.

分子線에피택셜 方法으로 成長한 I $n_{0.53}$GaTEX>$_{0.47}$As/InTEX>$_{0.52}$AlTEX>$_{0.48}$As/InP P-HEMT 構造內의 V 및 X字形 缺陷에 關한 硏究 (A study on the V and X shpe defects in I $n_{0.53}$GaTEX>$_{0.47}$As/InTEX>$_{0.52}$AlTEX>$_{0.48}$As/InP P-HEMT structure grown by molecular beam epitaxy method)

  • 이해권;홍상기;김상기;노동원;이재진;편광의;박형무
    • 전자공학회논문지D
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    • 제34D권7호
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    • pp.56-61
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    • 1997
  • I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A $l_{0.48}$As pseudomorphic high electron mobility transistor (P-HEMT) structures were grown on semi-insulating InP substrates by molecular beam epitzxy method. The hall effect measuremetn was used to measure the electrical properties and the photoluminescence (PL) measurement was used to measure the electrical properties and the photoluminescence(PL) measurement for optical propety. By the cross-sectional transmission electron microscopy (XTEM) investigation of the V and X shape defects including slip with angle of 60.deg. C and 120.deg. C to surface in the sampel, the defects formation mecahnism in the I $n_{0.52}$A $l_{0.48}$As epilayers on InP substrates could be explained with the different thermal expansion coefficients between I $n_{0.52}$A $l_{0.48}$As epilayers and InP substrate.d InP substrate.

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Comparison between Water and N-Tetradecane as Insulation Materials through Modeling and Simulation of Heat Transfer in Packaging Box for Vaccine Shipping

  • Dao, Van-Duong;Jin, Ik-Kyu;Hur, Ho;Choi, Ho-Suk
    • 청정기술
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    • 제22권1호
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    • pp.45-52
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    • 2016
  • This study reports on the modeling and simulation of heat transfer in packaging boxes used for vaccine shipping. Both water and n-tetradecane are used as primary insulation materials inside a multi-slab system. The one-dimensional model, which is a spherical model using a radius equivalent to the rectangular geometry of container, is applied in this study. N-tetradecane with low thermal diffusivity and proper phase transition temperature exhibits higher heat transfer resistance during both heating and cooling processes compared to water. Thus, n-tetradecane is a better candidate as an insulating material for packaging containers for vaccine shipping. Furthermore, the developed method can also become a rapid and economic tool for screening appropriate phase change materials used as insulation materials with suitable properties in logistics applications.

광발광 측정으로부터 얻어진 $ZnIn_2Se_4$ 박막의 열처리 효과 (Effect of thermal annealing for $ZnIn_2Se_4$ thin films obtained by photoluminescience measurement)

  • 홍광준
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.120-121
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    • 2009
  • Single crystalline $ZnIn_2Se_4$ layers were grown on thoroughly etched semi-insulating GaAs(100) substrate at $400^{\circ}C$ with hot wall epitaxy (HWE) system by evaporating, $ZnIn_2Se_4$ source at $630^{\circ}C$. After the as-grown $ZnIn_2Se_4$ single crystalline thin films was annealed in Zn-, Se-, and In-atmospheres, the origin of point defects of $ZnIn_2Se_4$single crystalline thin films has been investigated by the photoluminescence(PL) at 10 K The native defects of $V_{Zn}$, $V_{Se}$, $Zn_{int}$ and $Se_{int}$ obtained by PL measurements were classified as a donors or acceptors type. And we concluded that the heat-treatment in the Se-atmosphere converted $ZnIn_2Se_4$ single crystalline thin films to an optical p-type. Also, we confirmed that In in $ZnIn_2Se_4$/GaAs did not form the native defects because In in $ZnIn_2Se_4$ single crystalline thin films existed in the form of stable bonds.

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