• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Applied Chemistry for Engineering
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• v.35 no.2
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• pp.140-147
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• 2024

In order to increase the utilization of biomass, an electrochemical performance was considered after manufacturing a carbon anode material (SV-C) for a Setaria viridis-based lithium ion secondary battery through a heat treatment process. When the heat treatment temperature of the Setaria viridis is as low as 750 ℃, the capacitance (1003.3 mAh/g, at 0.1 C) is high due to the negative (-) charge of oxygen present on the surface attracting lithium, along with the low crystallinity and high specific surface area (126 m²/g), but the capacity retention rate is believed to be as low as 61.0% (at 500 cycles and 1 C). In addition, it was confirmed that when the heat treatment temperature increased to 1150 ℃, the carbon layer was condensed to be excellent in arrangement, and the structural defects were reduced, resulting in a significant reduction in the specific surface area (32 m²/g) of the pores. Furthermore, when the surface defects of the anode material are reduced and the crystallinity is increased, the capacity retention rate is as high as 89.7% (at 500 cycles and 1 C), but the degree of defects is small, the active point is reduced, and the specific capacity is considered to be very low at 471.7 mAh/g. In the scope of this study, it was found that in the case of the Setaria viridis-based carbon anode material manufactured according to the heat treatment temperature, the surface oxygen content and crystallinity have higher reliability on the electrochemical properties of the anode material than the specific surface area.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.225-229
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• 2011

In this study, capacitive type pressure sensors based on low temperature co-fired ceramics (LTCC) technology for environmental monitoring were demonstrated. The LTCC is one of promising technology than is based one since it has many advantages (e.g., low cost production, high manufacturing yields and easy realizing 3D structure etc.) for sensor application. Especially, it has good mechanical and chemical properties for robust environmental application. The 3D LTCC diaphragm with thickness of 400 ${\mu}m$ were fabricated by laminating 4 green sheets using commercial powder (NEG, MLS 22C). To evaluate the sensing properties of the different cavity areas, two types of diaphragm which had different cavity areas with 25, 49 $mm^2$ respectively, were fabricated. To realize capacitive type pressure sensor, the Au top electrode was fabricated using thermal evaporator and the bottome electrode was compressed using aluminium foil. The sensing properties of the fabricated sensors showed linear characteristic under different pressure (0~30 psi) using pressure measurement system.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.29 no.9
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• pp.472-481
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• 2017

Radiant floor heating systems have been used as common heating supply systems in most residential buildings in Korea. Since the system uses a floor as thermal storage, proper control strategy should be adopted to avoid over-or under-heating problems. So far, studies related to control of the floor heating system have been conducted based on computer simulations. The active layer in TRNSYS is known for its usability as a floor heating system model and is integrated with the TRNSYS building model (Type 56). However, floor heating system simulations with the active layer are operated only if pre-defined minimum mass flow rate is ensured. This study proposes a simple RC (Resistance-Capacitance) model for radiant floor heating systems. Model parameters such as Rs and Cs are defined by optimization. The active layer, in this study, is used as the target system to search for optimal values. A TRNOPT optimization tool was used to conduct optimization under given simulation conditions. The RC model with optimal parameters are tested in other mass flow rates that were not used during optimization. Results reveal the RC model describes the active layer with successfully optimized model parameters. The RC model has fewer model limitations, and is expected to be used for various target systems, e.g. experimental data of a real radiant heating system.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.299-299
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• 2016

SiC는 넓은 에너지갭 (Eg=~3.4 eV)을 갖는 반도체로써, 고전압, 고온에서 동작이 가능하여 기존의 Si기반의 파워디바이스를 대체하기 위한 물질로 많은 연구가 이루어지고 있다. 파워 디바이스의 성능 향상을 위해서는 기판과 절연체 사이의 계면에 생성되는 계면 결함을 감소시켜야 한다. 따라서 본 연구에서는 SiC 기판에 high-k 물질인 HfO2를 증착하여 HfO2/SiC 계면에 유도된 결함을 분석하고 이를 감소시킬 수 있는 방법에 대한 연구를 수행하였다. HfO2 박막은 atomic-layer-deposition (ALD) 방법을 이용하여 SiC 기판 위에 $200^{\circ}C$에서 증착하였다. HfO2 박막 증착 후 NH3 분위기에서 rapid thermal annealing 방법을 이용하여 $600^{\circ}C$에서 1분 동안 열처리 진행하였다. Current-voltage (I-V) 측정을 통해 열처리 전 HfO2/SiC의 절연파괴 전압이 약 8.3 V 임을 확인하였다. NH3 열처리 후 HfO2/SiC의 절연파괴 전압이 10 V로 증가하였으며 누설 전류가 크게 감소하는 것을 확인하였다. 또한 capacitance-voltage (C-V) 측정을 통해 열처리 후 flat band voltage가 negative 방향에서 positive 방향으로 이동함을 확인하였고, 이를 통해 NH3 열처리 방법이 HfO2/SiC 계면에 존재하는 결함을 감소시킬 수 있음을 확인하였다. 전자 구조상의 conduction band edge에 존재하는 결함 준위를 분석하기 위해 x-ray absorption spectroscopy (XAS) 분석을 실시하였고, 열처리 전 HfO2/SiC 계면에 많은 결함 준위가 존재함을 확인하였으며, x-ray photoelectron spectroscopy (XPS) 분석을 통해 이 결함 준위가 oxygen deficiency state과 관련됨을 알 수 있었다. NH3 열처리 후 결과와 비교해보면, oxygen deficiency state가 감소함을 확인하였으며 이로 인해 conduction band edge에 존재하는 결함 준위가 감소함을 알 수 있었다. 따라서, NH3 열처리 방법을 이용하여 HfO2/SiC 계면에 존재하는 결함을 감소시킬 수 있으며, HfO2/SiC의 물리적, 전기적 특성을 향상시킬 수 있다는 결과를 도출하였다.

• Korean Journal of Materials Research
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• v.19 no.2
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• pp.90-94
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• 2009

The development of low-k materials is essential for modern semiconductor processes to reduce the cross-talk, signal delay and capacitance between multiple layers. The effect of the $CH_4$ concentration on the formation of SiOC(-H) films and their dielectric characteristics were investigated. SiOC(-H) thin films were deposited on Si(100)/$SiO_2$/Ti/Pt substrates by plasma-enhanced chemical vapor deposition (PECVD) with $SiH_4$, $CO_2$ and $CH_4$ gas mixtures. After the deposition, the SiOC(-H) thin films were annealed in an Ar atmosphere using rapid thermal annealing (RTA) for 30min. The electrical properties of the SiOC(-H) films were then measured using an impedance analyzer. The dielectric constant decreased as the $CH_4$ concentration of low-k SiOC(-H) thin film increased. The decrease in the dielectric constant was explained in terms of the decrease of the ionic polarization due to the increase of the relative carbon content. The spectrum via Fourier transform infrared (FT-IR) spectroscopy showed a variety of bonding configurations, including Si-O-Si, H-Si-O, Si-$(CH_3)_2$, Si-$CH_3$ and $CH_x$ in the absorbance mode over the range from 650 to $4000\;cm^{-1}$. The results showed that dielectric properties with different $CH_4$ concentrations are closely related to the (Si-$CH_3$)/[(Si-$CH_3$)+(Si-O)] ratio.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.36.2-36.2
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• 2009

Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.140-140
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• 2009

The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. Insulators investigated as a buffer insulator in a MFIS structure, include $Ta_2O_5$, $HfO_2$, and $ZrO_2$ which are mainly high-k dielectrics. In this study, we prepared the Dy-doped $La_2O_3$ solution buffer layer as an insulator. To form a Dy-doped $La_2O_3$ buffer layer, the solution was spin-coated on p-type Si(100) wafer. The coated Dy-doped $La_2O_3$ films were annealed at various temperatures by rapid thermal annealing (RTA). To evaluate electrical properties, Au electrodes were thermally evaporated onto the surface of the samples. Finally, we observed the surface morphology and crystallization quality of the Dy-doped $La_2O_3$ on Si using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/Dy-doped La2O3/Si structure were measured.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.2-65
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• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.