• 전자공학회논문지B
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• 제31B권9호
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• Journal of Information Processing Systems
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• 제7권2호
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• pp.363-384
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• 2011

As the complexity of software is increasing, generating an effective test data has become a necessity. This necessity has increased the demand for techniques that can generate test data effectively. This paper proposes a test data generation technique based on adequacy based testing criteria. Adequacy based testing criteria uses the concept of mutation analysis to check the adequacy of test data. In general, mutation analysis is applied after the test data is generated. But, in this work, we propose a technique that applies mutation analysis at the time of test data generation only, rather than applying it after the test data has been generated. This saves significant amount of time (required to generate adequate test cases) as compared to the latter case as the total time in the latter case is the sum of the time to generate test data and the time to apply mutation analysis to the generated test data. We also use genetic algorithms that explore the complete domain of the program to provide near-global optimum solution. In this paper, we first define and explain the proposed technique. Then we validate the proposed technique using ten real time programs. The proposed technique is compared with path testing technique (that use reliability based testing criteria) for these ten programs. The results show that the adequacy based proposed technique is better than the reliability based path testing technique and there is a significant reduce in number of generated test cases and time taken to generate test cases.

• 정보과학회 논문지
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• 제42권11호
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• pp.1386-1396
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• 2015

안드로이드(Android) 어플리케이션(앱)의 신뢰성과 사용성 검증을 위해, 앱의 기능 검사와 크래쉬(Crash) 탐지 등을 위한 다양한 GUI 테스팅(Graphical User Interface Testing) 기법이 널리 사용되고 있다. 그 중 모델 기반(Model-based) GUI 테스팅 기법은 GUI 모델을 이용해 테스트 케이스를 생성하기 때문에, 기법의 유효성(Effectiveness)은 기반 모델의 정확도에 의존적이다. 따라서 모델 기반 기법의 유효성 향상을 위해서는 테스트 대상 앱의 행위를 충분히 반영할 수 있는 모델 생성 기법이 필요하며, 이를 위해 본 연구에서는 GUI 상태를 정밀하게 구분하는 계층적 화면 비교 기법을 통해 테스팅의 유효성과 효율성을 향상시키고자 한다. 또한, 기존 연구 기법과의 비교 실험을 통해 제안 기법이 유효한 모델의 효율적 생성을 가능하게 함을 확인함으로써, 모델 기반 안드로이드 GUI 테스팅의 성능 향상 가능성을 제시한다.

• 한국가스학회지
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• 제16권1호
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• pp.22-25
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• 2012

Welding and/or fusion in polyethylene(PE) system made on site is focused on the control of the welding or fusion process to follow proper procedure. The process control is important, but it is not sufficient for the long term reliability of a pipe system. To achieve the rate of failure close to zero, Non Destructive Testing(NDT) is necessary in addition to joining process control. For electrofusion joints several non-destructive testing methods are available. The ultrasonic phased array technique is possible to detect various defects including wire deviations and regions with lack of fusion. In this studies, testing was carried to detect the defect after electrofusion joining of polyethylene piping is utilized by the ultrasonic phased array technique. From testing data, ultrasonic phased array technique is recommended as a reliable non-destructive testing method.

• Journal of Information Processing Systems
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• 제6권1호
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• pp.21-32
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• 2010

Software maintenance is one of the major activities of the software development life cycle. Due to the time and cost constraint it is not possible to perform exhaustive regression testing. Thus, there is a need for a technique that selects and prioritizes the effective and important test cases so that the testing effort is reduced. In an analogous study we have proposed a new variable based algorithm that works on variables using the hybrid technique. However, in the real world the programs consist of multiple modules. Hence, in this work we propose a regression testing algorithm that works on interprocedural programs. In order to validate and analyze this technique we have used various programs. The result shows that the performance and accuracy of this technique is very high.

• 전자공학회논문지A
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• 제32A권12호
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• 비파괴검사학회지
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• 제28권1호
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• pp.64-69
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• 2008

압력용기 및 구조물 용접부의 내부결함을 검출하기 위해서는 방사선투과시험과 초음파탐상시험을 시행한다. 그러나 방사선투과시험은 방사선 노출 위험성과 필름 현상처리 소요 등으로 결과의 확인에 상대적으로 긴 시간이 소요되어 제작 공정에 영향을 준다. 일반적인 수동 초음파탐상시험은 결과의 재현이 용이하지 않으며 검사자의 기량에 대한 의존도가 높다는 문제점을 가지고 있다. 이에 대한 대안으로 자동 초음파탐상시험 기법의 하나인 TOFD의 적용이 확산되고 있다. 본 연구는 결함을 포함한 시험편에 대하여 방사선투과 시험과 TOFD 기법을 적용하고 비교한 결과를 기술하였다. TOFD 기법은 초음파 시험기법의 객관적 신뢰도 향상에 기여하게 될 것으로 판단된다.

• Journal of Information Processing Systems
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• 제6권2호
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• pp.235-252
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• 2010

Regression testing is a very costly process performed primarily as a software maintenance activity. It is the process of retesting the modified parts of the software and ensuring that no new errors have been introduced into previously tested source code due to these modifications. A regression test selection technique selects an appropriate number of test cases from a test suite that might expose a fault in the modified program. In this paper, we propose both a regression test selection and prioritization technique. We implemented our regression test selection technique and demonstrated in two case studies that our technique is effective regarding selecting and prioritizing test cases. The results show that our technique may significantly reduce the number of test cases and thus the cost and resources for performing regression testing on modified software.

• 대한전자공학회논문지SD
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• 제43권5호
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• pp.34-47
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• 2006

본 논문에서는 무선 트랜시버 구성소자들의 완제품 테스팅을 용이하게 할 수 있는 새로운 테스팅 기법을 제안하였다. 즉 RF 집적회로에 존재하는 고장들에 대하여 설계사양의 정보를 포함하는 구간고장모델(band fault model)을 제안하고 이 구간고장모델들의 변화를 회로의 출력에서 그대로 관찰할 수 있도록 함으로써 시간영역에서 설계사양에 대한 테스트를 용이하게 할 수 있는 방식을 제시하였다. 이 방식은 주파수 영역에서 테스트를 행하는 기존의 설계사양 테스트를 시간영역에서 용이하게 테스트할 수 있도록 함으로써 고가의 테스트 장비가 필요 없으며 테스트 시간이 단축되는 장점이 있다. 본 논문에서 제시된 테스팅 기법을 5.25 GHz 저잡음증폭기의 테스트에 적용하여 설계사양을 고려한 시간영역 테스팅 기법이 저잡음증폭기를 비롯한 RF 집적회로의 테스트에 매우 효과적임을 입증하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.