• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.4
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• Journal of Internet Computing and Services
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• v.5 no.1
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• pp.67-84
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• 2004

Real-time database systems (RTDBS) are database systems whose transactions are associated with timing constraints such as deadlines. Therefore transaction needs to be completed by a certain deadline. Besides meeting timing constraints, a RTDBS needs to observe data consistency constraints as well. That is to say, unlike a conventional database system, whose main objective is to provide fast average response time, RTDBS may be evaluated based on how often transactions miss their deadline, the average lateness or tardiness of late transactions, the cost incurred in transactions missing their deadlines. Therefore, in RTDBS, transactions should be scheduled according to their criticalness and tightness of their deadlines, even If this means sacrificing fairness and system throughput, And It always must guarantee preceding process of the transaction with the higher priority. In this paper, we propose an efficient real-time scheduling algorithm (Multi-level EFDF) that alleviates problems of the existing real-time scheduling algorithms, a real-time concurrency control algorithm(2PL-FT) for firm and soft real-time transactions. And we compare the proposed 2PL F[ with AVCC in terms of the restarting ratio and the deadline missing ratio of transactions. We show through experiments that our algorithms achieve good performance over the other existing methods proposed earlier.

• Journal of Korean Academy of Nursing Administration
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• v.20 no.4
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• pp.353-361
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• 2014

Purpose: The aim of this study was to compare job satisfaction, quality of life (QOL), incident report rate and overtime hours for 12-hour shifts and for 8-hour shifts in a pediatric intensive care unit (PICU). Methods: A descriptive survey was conducted with a convenience sample of 36 staff nurses from a PICU in a regional hospital in Korea. Data were collected using self-administrated questionnaires regarding job satisfaction and QOL at 6 months before and after the beginning of 12-hour shifts. Incident report rate and overtime hours for both 12-hour and 8-hour shifts were compared. Comparisons were made using $x^2$-test, paired t-test and Mann-Whitney U test. Results: After 12-hour shifts were initiated, job satisfaction significantly increased (t=3.93, p<.001) and QOL was higher for nurses on 12-hour shifts compared to 8-hour (t=7.83, p<.001). There was no statistically significant change in incident report rate ($x^2=0.15$, p=.720). The overtimes decreased from $36.3{\pm}34.7$ to $17.3{\pm}34.9$ minutes (Z=-8.91, p<.001). Conclusion: These results provide evidence that 12-hour shifts can be an effective ways of scheduling for staff nurses to increase job satisfaction and quality of life without increasing patient safety incidents or prolonged overtime work hours.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1134-1143
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• 2000

We propose a scheduling algorithm, Bandwidth Allocation Scheme (BAS), that guarantees bounded delay in a switching node. It is based on the notion of the GPS (Generalized Processor Sharing) mechanism, which has clarified the concept of fair queueing with a fluid-flow hypothesis of traffic modeling. The main objective of this paper is to determine the session-level weights that define the GPS sewer. The way of introducing and derivation of the so-called system equation' implies the approach we take. With multiple classes of traffic, we define a set of service curves:one for each class. Constrained to the required profiles of individual service curves for delay satisfaction, the sets of weights are determined as a function of both the delay requirements and the traffic parameters. The schedulability test conditions, which are necessary to implement the call admission control, are also derived to ensure the proposed bandwidth allocation scheme' be able to support delay guarantees for all accepted classes of traffic. It is noticeable that the values of weights are tunable rather than fixed in accordance with the varying system status. This feature of adaptability is beneficial towards the enhanced efficiency of bandwidth sharing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1B
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• pp.73-85
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• 2004

SIn this paper, we introduce our experience for designing and implementing new concept of a global XML-based Peer-to-Peer (P2P) engine to support various P2P applications, and interconnection among PC, Web and mobile computing environments. The proposed P2P engine can support to heterogeneous data exchanges and web interconnection by facilitating with the text-base XML while message exchange are necessary. It is also to provide multi-level security functions as well as to apply different types of security algorithms. The system consist of four modules; a message dispatcher to scheduling and filtering the message, a SecureNet to providing security services and data transmission, a Discovery Manager to constructing peer-to-peer networking, and a Repository Manager to processing data management including XML documents. As a feasibility test, we implement various P2P services such as chatting as a communication service, white-board as an authoring tool set during collaborative working, and a file system as a file sharing service. We also compared the proposed system to a Gnutella in order to measure performance of the systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.3
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• pp.141-152
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• 2007

In this paper, we present a network-oriented lightweight real-time system, which is composed of an event-driven operating system called the Embedded Lightweight Operating System (ELOS) and a generic multi hop ad hoc routing protocol suite. In the ELOS, a conditional preemptive FCFS scheduling method with a guaranteed time slot is designed for efficient real-time processing. For more elaborate configurations, we reinforce fault tolerance by supplementing semi-auto configuration using wireless agent nodes. The developed hardware platform is also introduced, which is a scalable prototype constructed using off-the-shelf components. In addition, in order to evaluate the performance of the proposed system, we developed a ubiquitous network test-bed on which several experiments with respect to various environments are conducted. The results show that the ELOS is considerably favorable for tiny ubiquitous networked systems with real-time constraints.

• Proceedings of the Korea Concrete Institute Conference
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• 2006.05a
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• pp.5-21
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• 2006

Traditional standards and specifications for concrete have largely been prescriptive, (or prescription-based), and can sometimes hinder innovation and in particular the use of more environmentally friendly concretes by requiring minimum cement contents and SCM replacement levels. In December 2004, the Canadian CSA A23.1-04 standard was issued which made provisions (a) for high-volume SCM concretes, (b) added new performance requirements for concrete, and (c) clearly outlined the requirements and responsibilities for use in performance-based concrete specifications. Also, in December 2003, the CSA A3000 Hydraulic Cement standard was revised. It (a) reclassified the types of cements based on performance requirements, with both Portland and blended cements meeting the same physical requirements, (b) allows the use of performance testing for assessing sulphate resistance of cementitious materials combinations, (c) includes an Annex D, which allows performance testing of new or non-traditional supplementary cementing materials. From a review of international concrete standards, it was found that one of the main concerns with performance specifications has been the lack of tests, or lack of confidence in existing tests, for judging all relevant performance concerns. Of currently used or available test methods for both fresh, hardened physical, and durability properties, it was found that although there may be no ideal testing solutions, there are a number of practical and useful tests available. Some of these were adopted in CSA A23.1-04, and it is likely that new performance tests will be added in future revisions. Other concerns with performance standards are the different perspectives on the point of testing for performance. Some concrete suppliers may prefer processes for both pre-qualifying the plant, and specific mixtures, followed only with testing only 'end-of-chute' fresh properties on-site. However, owners want to know the in-place performance of the concrete, especially with high-volume SCM concretes where placing and curing are important. Also, the contractor must be aware of, and share the responsibility for handling, constructability, curing, and scheduling issues that influence the in-place concrete properties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.89-96
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• 2005

In this paper, we propose a customer premise platform for processing multimedia data service on the ATM network. The proposed platform has a specific AAL2 processor that includes AAL2 protocol and scheduler algorithm so as to off-load large potion of burden from host processor and make it easy to process multimedia data from the ATM network in real time compared with conventional platform in which AAL/ATM tasks are processed by software. The ATS scheduler that is implemented based on 2-level time slot ring provides a simple and efficient method for scheduling data of VBR-rt, UBR and CBR traffics. TMS320C5402 DSP is used to process voice-related tasks such as voice compression and voice packet manupulation and AAL2 processor is implemented on $0.35\;{\mu}m$ process line. We implemented the customer premise equipment for VoDSL service and tested the proposed platform on a test bed network. The experimental results show that the proposed equipment has the call success rate of $97\%$ at least and provides voice service of toll-qualify.

• Journal of IKEEE
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• v.19 no.3
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• pp.385-391
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• 2015

In this paper, we analyze the communication performance in a time synchronous multi-channel environment and deal with a packet collision avoidance technique to improve it based on IEEE1609.4 for increasing the efficiency of the control channel IEEE802.11p WAVE communication system. In previous works, they tried to solve this problem by message scheduling method on application layer software or changing the value of the random back-off optionally Contention Window. In this paper, we propose a method for adjusting the Channel Guard Interval for packet collision avoidance. The performance was evaluated by the actual vehicle test. The result was confirmed performance over 90% PDR(Packet Delivery Ratio).