• The KIPS Transactions:PartD
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• v.16D no.3
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• pp.371-380
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• 2009

Recently, lots of research on automated test data generation has been actively done. However, techniques for automated test data generation presented so far have been proved ineffective for programs with flag variables. It can present problems when considering embedded systems such as engine controllers that make extensive use of flag variables to record state information concerning devices. This paper introduces a technique for generating test data effectively for programs with flag variables. The presented technique transforms the test data generation problem into a SAT(SATisfiability) problem and makes advantage of SAT solvers for automated test data generation(ATDG). For the ends, we transform a program under test into Alloy which is the first-order relational logic and then produce test data via Alloy analyzer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1118-1127
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• 1990

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.

• Management Science and Financial Engineering
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• v.11 no.2
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• pp.85-103
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• 2005

In this paper, we consider the routing and wavelength assignment problem in survivable WDM transport network without wavelength conversion. We assume the single-link failure and a path protection scheme in optical layer. When a physical network and a set of working paths are given, the problem is to select a link-disjoint protection path for each working path and assign a wavelength for each working and protection path. We give an integer programming formulation of the problem and propose an algorithm to solve it. Though the formulation has exponentially many variables, we solve the linear programming relaxation of it by using column generation technique. We devise a branch-and price algorithm to solve the column generation problem. After solving the linear programming relaxation, we apply a variable fixing procedure combined with the column generation to get an integral solution. We test the proposed algorithm on some randomly generated data and test results show that the algorithm gives very good solutions.

• Journal of Engineering Education Research
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• v.2 no.1
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• pp.17-23
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• 1999

Internet application for education has drawn interests in recent time. Usually the method of communication was unidirectional, which means teachers posted educational material on a server and students received them. Even the usage of WWW can't overcome the restriction of unidirectional communication problem. In order to solve this problem, researchers and commercial vendors began to provide packages for bidirectional solution. Those packages are course test generation and evaluation packages using Internet. They provide functionalities of problem generation and score management. In this paper some of those packages are reviewed, and the functionalities of JPGEM (Java Problem Generation and Evaluation Module), which is developed by the author of this paper, are discussed in detail.

• Journal of Internet Computing and Services
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• v.9 no.2
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• pp.89-105
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• 2008

So far, most of research on automated test data generation(ATDG) deals with programs without pointers. Recently, few works hove been done on ATDG in the presence of pointers, but they ore path-oriented techniques which require the specification of on entire program path to be tested or a program to be executed. This paper presents a new technique for generating test data even without specifying a program path completely. The presented technique is a static technique which transforms the test data generation problem into a SAT(SATisfiability) problem and makes advantage of SAT solvers for ATDG. For the ends, we transform a program under test into Alloy which is the first-order relational logic and then produce test data via Alloy analyzer.

• ETRI Journal
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• v.23 no.3
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• pp.138-149
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• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• Journal of the Korean Operations Research and Management Science Society
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• v.25 no.3
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• pp.17-33
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• 2000

We consider the Steiner tree packing problem. For a given undirected graph G =(V, E) with positive integer capacities and non-negative weights on its edges, and a list of node sets(nets), the problem is to find a connection of nets which satisfies the edge capacity limits and minimizes the total weights. We focus on the switchbox routing problem in knock-knee model and formulate this problem as an integer programming using Steiner tree variables. The model contains exponential number of variables, but the problem can be solved using a polynomial time column generation procedure. We test the algorithm on some standard test instances and compare the performances with the results using cutting plane approach. Computational results show that our algorithm is competitive to the cutting plane algorithm presented by Grotschel et al. and can be used to solve practically sized problems.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.124-127
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• 2001

We consider the routing and wavelength assignment problem in survivable WDM transport network without wavelength conversion. We assume the single-link failure and a path protection scheme in optical layer. When a physical network and a set of working paths are given, the problem is to select a link-disjoint protection path for each working path and assign a wavelength for each working and protection path. We give an integer programming formulation of the problem and propose an algorithm to solve it based on column generation technique and variable fixing. We devise a branch-and-price algorithm to solve the column generation problem. We test the proposed algorithm on some randomly generated data and test results show that the algorithm gives very good solutions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.