• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.234-237
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• 2000

In this paper, a method to implement new Quasi-SOI LDMOSFET is introduced and the electrical characteristics of the device are studied. Key process steps of the device are explained briefly. By performing process and device simulations, electrical characteristics of the device are investigated, with emphasis on the optimization of the tilt angle of p$\^$0/ channel region. The electrical properties of the Quasi-SOI device are compared with those of bulk and SOI devices with the same process parameters. Simulated device characteristics are threshold voltage, off-state leakage current, subthreshold swing, DIBL, output resistance, lattice temperature, I$\_$D/-V$\_$Ds/, and cut-off frequency.

• 설비공학논문집
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• 제23권4호
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• pp.281-286
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• 2011

The objective of this study is to optimize the four-bed six-step pressure swing adsorption(PSA) process for high purity $CH_4$ recovery from the biogas. The effects of P/F(purge to feed) ratio and cycle time on the process performance were evaluated. The cyclic steady-states of PSA process were reached after 12 cycles. The purity and recovery rate of product gas, pressure and temperature changes were constant as the cycle repeated. It was shown that the P/F ratio gave significant effect on the product recovery rate by increasing the amount of purge gas in purge and regeneration step. The optimal P/F ratio was found to be 0.08. As the cycle time increased, the product purity decreased by increasing the feed gas flow rate. It was found that the optimal operating conditions were P/F ratio of 0.08 and total cycle time of 1,440 seconds with the purity of 97%.

• 공업화학
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• 제17권2호
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• pp.201-209
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• 2006

활성탄과 제올라이트 13X를 충진시킨 흡착탑에 흡착질인 벤젠을 포화 흡착시킨 후 여러 가지 탈착 방법에 대한 효율을 살펴보았다. 뜨거운 수증기에 의한 탈착, 세정 기체에 의한 탈착, 진공에 의한 탈착 등을 실험하였고, 그 결과 뜨거운 수증기에 의한 탈착이 가장 좋은 탈착 방법으로 판단되었다. 또한 뜨거운 수증기는 흡착탑 내의 온도를 상승시키면서 탈착을 야기시키고 수증기 탈착 과정 이후에는 건조 공정이 수반되어야만 효율이 높아짐을 알 수 있었다. 건조 공정이 수반되지 않을 경우는 수증기가 추후에 흡착을 방해하는 결과를 초래하였다. 진공에 의한 탈착은 효과가 매우 적은 것으로 나타났는데 이로부터 벤젠의 경우에 압력 변화에 의한 탈착 보다는 온도 변화에 의한 탈착이 더 효과적인 것으로 판단되었다. 세정 기체에 의한 탈착에서는 진공 탈착과 함께 이루어질 때 좋은 탈착 성능이 나타남을 알 수 있었다.

• 공업화학
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• 제20권6호
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• pp.663-669
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• 2009

지구온난화에 가장 큰 영향을 미치는 이산화탄소를 연소 후 배가스로부터 흡착 분리하기 위한 허니컴 흡착소자의 제조 및 그 특성에 관한 것이다. 고온사용이 가능하도록 세라믹쉬트, 활성탄소 쉬트를 사용하여 허니컴을 제조하였고 그 위에 Na-X 제올라이트를 코팅하였다. 또한 Na-X 제올라이트를 포함시킨 제올라이트 쉬트를 사용하여 허니컴 흡착제를 제조하였다. 이들 세 가지 허니컴 흡착제에 대하여 이산화탄소 흡착량, 표면특성 그리고 16% 이산화탄소 혼합가스를 공급하여 파과특성을 분석하였다. 또한 가열재생에 따른 이산화탄소 농축특성과 가열시 허니컴 흡착제의 온도변화를 분석하여 열스윙 흡착 분리공정에서의 우월성을 비교 분석하였다. 이들 허니컴을 사용한 흡착파과실험 결과를 바탕으로 하여 회전식 흡착 농축공정의 적용 가능예를 보여주었다.

• 한국대기환경학회지
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• 제26권3호
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• pp.286-297
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• 2010

This study deals with the effect of pretreatment on the $CO_2$ adsorption capacity of zeolitic adsorbents including a commercial A-type zeolite and cation exchanged adsorbents. The pre-heating could change the intrinsic properties such as specific surface area and adsorption capacity of the adsorbent. As a result of the experiment, the moisture previously filled inside might affect the potential adsorption capacity of the adsorbent, and could be disappeared throughout the heat treatment. An optimum pretreatment temperature for the test adsorbent was found to be $400^{\circ}C$, at which temperature enabled more than 90% refreshment. Precise examination through the TPD test showed that the TSA (Temperature Swing Adsorption) process would be desirable in dry adsorption of $CO_2$.

• 한국전기전자재료학회논문지
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• 제25권7호
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• pp.521-524
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• 2012

We report on variations of electrical properties with different active layer thickness and post-annealing temperature in amorphous In-Ga-Zn-O (IGZO) thin-film transistors (TFTs). In particular, subthreshold swing (SS) of the IGZO-TFTs was improved as increasing the active layer thickness at an given post-annealing temperature, accompanying the negative shift in turn-off voltage. However, as increasing post-annealing temperature, only turn-off voltage was shifted negatively with almost constant SS value. The effect of the active layer thickness and post-annealing temperature on electrical properties, such as SS, field effect mobility and turn-off voltage in IGZO-TFTs has been explained in terms of the variation of trap density in IGZO channel layer and at gate dielectric/IGZO interface.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.97-101
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• 2017

In this paper, IGZO thin film transistor (TFT) was fabricated with cross-linked Poly (4-vinylphenol) (PVP) gate dielectric for flexible, transparent display applications. The PVP is one of the candidates for low-temperature gate insulators. MIM structure was fabricated to measure the leakage current and evaluate the insulator properties according to the annealing temperature. Low leakage current ( <0.1nA/cm2 @ 1MV/cm ) was observed at $200^{\circ}C$ annealing condition and decreases much more as the annealing temperature increases. The electrical characteristics of IGZO TFT such as subthreshold swing, mobility and ON/OFF current ratio were also improved, which shows that the performance of IGZO TFTs with PVP can be enhanced by reducing the amount of incomplete crosslinking in PVP.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1412-1413
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• 2011

Effects of thermal annealing on electrical characteristics of thin film transistors (TFTs) using hydrogenated zinc oxide (ZnO:H) films as active channel were extensively investigated. The ZnO:H films were deposited at room temperature by RF sputtering. The device parameters of the ZnO:H-based TFTs, such as threshold voltage ($V_{th}$), subthreshold swing (S.S.), and on-off current ratio ($I_{on}/I_{off}$), were characterized in terms of the annealing temperature as well as the gas flow ratio of $H_2$/Ar.

• Journal of Information Display
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• 제12권1호
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.