• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1691-1698
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• 1989

Gas sensing effects produced by adsorptive reaction between specimen surface and gases are expected to be influenced greatly by the state of the speimen surface. In this study, Co1-xMgxO ceramics oxygen sensors were prepared by pressing at 0.3-1.5ton/cm\ulcornerwith or without binder, intending to change porosity and average grain size on the surface purposely. The composition ratio of CoO to MgO was fixed at 1:1(mol.%). Microstructure of prepared Co0.5Mg0.5O ceramics were observed, the electrical properties and the sensitivity characteristics for oxygen gas were investigated in the device temperature range of 700-1000\ulcorner and for oxygen partical pressure range of 1-10**-4 atm. Temperature dependence of the resistivity of the specimen showed NTC behavior, average grain size increased and porosity decreased with increasing compaction pressure. The slope of the resistivity of the specimen on the oxygen partial pressure decreased with increasing average grain size and with decreasing porosity. Particularly, specimen pressed by 0.3 and 0.5 ton/cm\ulcornershowed the highest sensitivity to oxygen gas.

• 전자공학회논문지B
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• 제32B권1호
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• pp.73-84
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• 1995

New morphological positioning algorithm and inspection method are presented and compared with a method by means of the Hough transform. The positioning algorithm is the process of finding the center and the rotated angle of the surface mounted device (SMD). The inspection method is capable of detecting the location of broken or bent leads. In order to obtain the center and the orientation of the SMD rapidly, the Hough transform method utilizes feature points (concave points) and is executed on a DSP board. The proposed morphological method is implemented by using the morphological skeleton subsets, and an ultimate orientation is decided by the Hit-or-Miss transform (HMT). In the inspection process, two inspection methods also are presented. The first method utilizes the morphological methods, i.e., opening and closing. It is performed before the positioning process and called an initial inspection. The second method follows the positioning process and is performed by an inspection of intersections of rulers and the lead edge (or the skeleton). It is a ruling technique which is referred to as a detailed inspection. We find the morphological approach is preciser and faster than the Hough approach by the comparison of the proposed algorithms.

• 전자공학회논문지A
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• 제33A권7호
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• 전자공학회논문지C
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• 제36C권10호
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• pp.1-7
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• 1999

정보화시대가 도래함에 따라 기존의 종이문서 관리방식이 전자문서 관리방식으로 변하고 많은 응용 프로그램들이 인트라넷 기술을 사용하여 업무 효율을 높이고 있다. 본 논문은 인트라넷 환경에서 전자문서관리시스템의 설계 및 구현에 관한 것으로 사용자 및 일반관리자 시스템은 Internet Explorer 4.0을 기반으로 구현하여 하드웨어 특성에 따라 영향을 받던 클라이언트 시스템의 문제점을 해결하였다. 별도의 디바이스 드라이버가 필요한 스캔 스테이션과 전자문서관리시스템 서버는 TCP/IP를 통한 클라이언트/서버 시스템으로 구현하였다. 대용량의 데이터를 저장하는 주크박스는 표준 SCSI-ll를 지원하는 API를 구현하고 GUI는 Motif를 이용하여 구현함으로서 호환성과 편리성을 높였다.

• 전자공학회논문지A
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• 제32A권6호
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• pp.41-50
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• 1995

A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

• 대한전자공학회논문지
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• 제26권1호
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• pp.62-68
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• 1989

본 논문에서는 아날로그/디지탈 회로 구성시 입출력부는 바이폴라 소자로 내부의 논리회로 부분은 CMOS 소자로 높은 내압을 요구하는 부분에는 DMOS 소자를 이용할 수 있는, BCDMOS 공정 기술개발을 하고자 하였다. BCDMOS 제작 공정은 폴리게이트 p-well CMOS 공정을 기본으로 하였고, 소자설계의 기본개념은 공정흐름을 복잡하지 않게 하면서 바이폴라, CMOS, DMOS 소자 각각의 특성을 좋게하는데 두었다. 실험결과로서 바이폴라 npn 트랜지스터의 $h_{FE}$ 특성은 320(Ib-$10{\mu}A$)정도이며, CMOS 소자에서는 n-채자에서는 항복전압이 115V이상의 특성을 얻을 수 있었다.

• 전자공학회논문지D
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• 제35D권6호
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• pp.37-45
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• 1998

본 논문에서는 본 연구진이 개발 중인 INPROS 3차원 반도체 공정 시뮬레이터 시스템에 이온주입된 불순물의 과도 확산(TED, transient enhanced diffusion) 기능을 첨가하여 수행한 계산 결과를 발표한다. 실리콘 내부에 이온주입된 불순물의 재분포를 시뮬레이션하기 위하여, 먼저 몬테카를로 방법으로 이온주입 공정을 수행하였고, 유한요소법을 이용하여 확산 공정을 수행하였다. 저온 열처리 공정에서의 붕소의 과도 확산을 확인하기 위하여, 에피 성장된 붕소 에피층에 비소와 인을 이온 주입시킨 후, 750℃의 저온에서 2시간 동안 열처리 공정을 수행하였다. 3차원 INPROS 시뮬레이터의 결과와 실험적으로 측정한 SIMS 데이터와 그 결과가 일치함을 확인하였다. INPROS의 점결함 의존성 과도 증속 확산 모델과 소자 시뮬레이터인 PISCES를 이용하여 역 단채널 길이 효과(RSCE, reverse short channel effect)를 시뮬레이션하였다.

• 전자공학회논문지C
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• 제34C권11호
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• pp.66-75
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• 1997

We derive the system design parameters to implement the receiving system for the PCS mobile station to satisfy the J-sTD-018 which is the PCS mobile station(MS) minimum performance. Also we analyze the system performance and intermodulation spurious due to the values of a device cause the system performance degradation, is proposed. The simulation shows the receiver's maximum system noise figure to satisfy the receiver selectivity is approximately 11 dB. While the MS noise figure is 10dB with system margin 1 dB, the minimum selectivity is -71 dB at 1.25MHz frequency offset from the carrier frequency. And the input 3rd order intercept point of the MS class I and the MS class II~V is -9.5 dBm and -14dBm respectively. When the interference power level at the receiver is small, the receiver has better performance as we increase the gain of the LNA. However, when the interference level at the receiver is large, the receiver performance is heavily affected by the spurious as we increase the gain of the LNA. Thus, we proved the effectiveness of the LNA On/Off switching technique as to reduce the effect of the spurious.

• 대한전자공학회논문지
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• 제18권1호
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• pp.16-24
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• 1981

Delay-lock loop(DLL)는 상단관련이 있는 두 파형 사이의 지연차이를 추적하는한 최적장치이다. 본 논문에서는 지연시간이 n- 로 확장된 한 DLL의 구조와 동기상실 주파수등 저역주파수대의 성능이 해석되었다. 본 DLL은 correlator와 개선된 PN 신호장치로 구성되었으며,상관 특성은 확장된 S-커브의 형태를 가지고 있다. 잡음이 크더라도 추적범위와 초기동기시간이 좋은 특성을 가지고 있다. 3- DLL을 1- DLL과 비교하면 직렬동기방식에서 초기동기시간이 3배나 빠르며, doppler shift에 대한 저항이 2배나 큰 것으로 나타났다.