• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.57-64
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• 2002

The structure of conventional CAM(Content Addressable Memory) cell, used to Look-up table scheme in Huffman CODEC, is not performed by being separated in reading, writing and match operation. So, there is disadvantages that the control is complicated, and the floating states of match line force wrong operation to be happened in reading, writing operation. In this paper, in order to improve the disadvantages and proces the data fast, fast Look-up table is designed using DBLCAM(Dual Bit Line CAM)-performing the reading, writing operation and match operation independently and Two-port SRAM being more fast than RAM in an access speed. Look-up table scheme in Huffman CODEC, using DBLCAM and Two-port SRAM proposed in this paper, is designed in Cadence tool, and layout is performed in 0.6${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS full custom. And simulation is peformed with Hspice.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.3
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• pp.273-281
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• 2001

In this paper, we propose a CMAC(Cerebellar Model Articulation Controller) neural network for controlling a non-linear system. CMAC is a neural network that models the human cerebellum. CMAC uses a table look-up method to resolve the complex non-linear system instead of numerical calculation method. It is very fast learn compared with other neural networks. It does not need a calculation time to generate control signals. The simulation results show that the proposed CMAC controllers for a simple non-linear function and a DC Motor speed control reduce tracking errors and improve the stability of its learning controllers. The validity of the proposed CMAC controller is also proved by the real-time tension control.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.228-232
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• 2002

The rise throughput and the stability in the device fabrication can be obtained by applying chemical mechanical polishing(CMP) process in 0.18 ${\mu}m$ semiconductor device. However it does have various problems due to the CMP equipment. Especially, among the CMP components, process variables are very important parameters in determining removal rate and non-uniformity. In this paper, We studied the DOE(design of experiment) method for the optimized CMP process. Various process variations, such as table and head speed, slurry flow rate and down force, have investigated in the viewpoint of removal rate and non-uniformity. Through the above DOE results, we could set-up the optimal process parameters.

• Tribology and Lubricants
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• v.30 no.3
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• pp.139-145
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• 2014

Nowadays, most micro-patterns are manufactured during flow line production. However, a conventional rotary chemical mechanical polishing (CMP) system has a limited throughput for the fabrication of large and flexible electronics. To overcome this problem, we propose a novel linear roll-CMP system for the planarization of large-area electronics. In this paper, we present a statistical analysis on the linear roll-CMP process of copper-clad laminate (CCL) to determine the impacts of process parameters on the material removal rate (MRR) and its non-uniformity (NU). In the linear roll-CMP process, process parameters such as the slurry flow rate, roll speed, table feed rate, and down force affect the MRR and NU. To determine the polishing characteristics of roll-CMP, we use Taguchi's orthogonal array L16 (44) for the experimental design and F-values obtained by the analysis of variance (ANOVA). We investigate the signal-to-noise (S/N) ratio to identify the prominent control parameters. The "higher is better" for the MRR and "lower is better" for the NU were selected for obtaining optimum CMP performance characteristics. The experimental and statistical results indicate that the down force and roll speed mainly affect the MRR and the down force and table feed rate determine the NU in the linear roll-CMP process. However, over 186.3 N of down force deteriorates the NU because of the bending of substrate. Roll speed has little relationship to the NU and the table feed rate does not impact on the MRR. This study provides information on the design parameter of roll-CMP machine and process optimization.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.658-672
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• 2004

Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.277-280
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• 2001

This paper presents a speed sensorless implementation of digital speed control system of Surface Permanent-Magnet Synchronous Motor(SPMSM) drives with a direct torque control(DTC). The system presented are stator flux and torque observer of stator flux feedback control model that inputs are current and voltage sensing of motor terminal with estimated rotor angle for a low speed operating area, two hysteresis band controllers, an optimal switching look-up table, rotor speed estimator, and IGBT voltage source inverter by using fully integrated control software. The developed speed sensorless control system are shown a good motion control response characteristic results and high performance features using 1.0Kw purposed servo drive SPMSM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1096-1101
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• 2004

By a tremendous expansion of Internet users, there's a number effects that cause the phenomenon of bottlenecked switching packets from routers. In order to tear down this problem, distributed system is applicable to almost every highly performed router systems. The main processor of distributed system, which manages routing table, commands IPC to delivering the forwarding table line processor that eases functionalities of the router. This makes the system having wired-speed forwarding function based on the hardware so that the performance of the network can be enhanced. Therefore, IPC, which assign a part of router, is necessary to exchange data smoothly and the constitution of IPC using Ethernet is widely adapted as a method for saving investment. In this paper, R-IPC mechanism improve the packet-processing rate over 10% through changed from defect of conventional Ethernet IPC, that is, 2 layer processing to TCP/IP or UDP/ IP into 1 layer processing for efficient packet forwarding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.589-592
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• 2004

The CORDIC algorithm can be implemented very simple H/W, but needs a lot of latency to compute trigonometric function. The RA(Redundant Arithmetic) resolves this problem, but also has difficulty to determine the directions of micro-rotations. The pre-computed direction of micro-rotation algorithm relieves the RA of this matter. In this paper, we proposed the modified the pre-computed algorithm adopted with a table-lookup. Instead of reducing H/W complexity, its performance and calculation errors are improved.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.4
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• pp.81-86
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• 2013

For a 2-dimensional(2D) vibration milling, an excitation work-table was developed using two piezoelectric materials orthogonally arranged, where the trochoidal trajectory of a milling tool is combined with 2 dimensional elliptical vibration of a work-table. Applying 3kHz excitation frequency and 7~8mm amplitude of vibration to micro milling process with brass and nickel materials, the roughness in both bottom and side surface is much more improved compared to the surface by conventional milling process, which is attributed to decreased frictional force, increased cutting speed, and rubbing effect of a 2 dimensional vibration.