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A Hardware Cache Prefetching Scheme for Multimedia Data with Intermittently Irregular Strides  

Chon Young-Suk (충북대학교 컴퓨터과학과)
Moon Hyun-Ju (나사렛대학교 정보과학부)
Jeon Joongnam (충북대학교 전기전자컴퓨터공학부)
Kim Sukil (충북대학교 컴퓨터과학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.31, no.11, 2004 , pp. 658-672 More about this Journal
Abstract
Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).
Keywords
multimedia application; data cache prefetch; reference prediction table; streaming access pattern;
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Times Cited By KSCI : 2  (Citation Analysis)
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