• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.84-88
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of two fully differential transconductors and lowers supply voltage down to VT+2VDS,sat+VDS,triode. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25㎛ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7VP-P.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.625-629
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• 2003

멀티 레벨 인버터는 고 전력 시스템에서 많이 사용되고 있다. 일반적으로 멀티 레벨 인버터는 캐스케이드와 NPC(Nuetral Point clamped) 두 가지 회로 방식이 있다. 동일한 시스템 조건에서 두 인버터를 비교하여 어느 한 인버터의 특성이 좋은가를 분석하기 위해 동일 조건하에 인버터 구조에 따라서 회로방식이 THD에 어떠한 영향을 주는지에 대해서 시뮬레이션을 통하여 살펴보고, FMI(Fundamental Modulation Index, 기본파 변조 지수)에 따라 두 회로 방식에 대한 THD 변화를 레벨 수에 따라 분석하고자 한다. 인버터에 사용되는 PWM 방식으로는 멀티 캐리어 PWM을 사용하였다.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.789-792
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• 2003

본 논문은 고전력 응용에 적합한 3상 멀티레벨 AC/DC컨버터의 THD를 분석하였다 회로는 일반 적인 NPC (Neutral Point Clamped)컨버터 타입을 채택하였고, 3레벨과 5레벨의 레벨수 증가에 따른 고조파를 분석하여 THD를 해석하였다. 공간벡터 PWM은 레벨이 증가할수록 벡터 공간도 증가하므로 영역판별이 어렵다는 단점이 있어 멀티 캐리어 PWM 방법을 사용하여 시스템을 분석하였다.

• Journal of Power Electronics
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• v.16 no.2
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• pp.532-541
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• 2016

A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.13-15
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• 2001

본 논문은 최근 3년간 강원 영서 지역에서 실측한 전원의 고조파 함유량을 토대로 전압 고조파, 중성선 전류 고조파 및 고조파로 인한 역율 저하를 분석하였다. 전압 고조파의 종합 왜형율(THD)은 순시 측정시 적합율 88.5%, 24시간 측정시 42.9%로 나타났으며, 중성선 전류의 종합 왜형율은 1,000%를 상회하는 장소가 20%를 차지하고 있어 심각한 문제점들이 발생될 수 있음을 알았다. 또한, 종합 고조파 왜형율의 증가로 인한 역율 저하는 평균 2%정도 발생되었다.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 1998.04a
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• pp.141-146
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• 1998

This study investigated the evaluation method for the users' color preference of CRT monitors. And also the users' preference of the colors displayed on CRT monitor using the park's color reproduction system was evaluated. Subjects conducted a series of psychophysical experiments to compare the colors displayed on a CRT monitor using the park's system to the colors without the system, Three evaluation methods were investigated: comparing one colors of same hue with diverse luminance and saturation. the results showed that subjects preferred the colors reproduced using the park's system, and thd evaluation methods significantly affected thd color preference.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.284-285
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• 2018

최근 전력품질 향상을 위해 계통전류에 대한 THD 규제가 강화되고 있음에 따라 THD와 누설전류의 개선 문제가 대두되고 있다. 단상 계통연계형 ESS에서는 흔히 인버터와 DC-DC컨버터를 사용하여 배터리를 충 방전 하는데, 이때 단상 인버터의 대지누설전류 또한 개선이 필요하다. 단상 인버터의 누설전류는 모듈레이션 방식을 변경함에 따라 차이가 나타난다. 따라서 본 논문에서는 단상 풀-브릿지 인버터의 유니폴라(Unipolar) 모듈레이션과 바이폴라(Bipolar) 모듈레이션 방버에 따른 누설전류의 크기를 PSIM을 통한 시뮬레이션과 실험을 통하여 비교 분석하였다.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.3
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• pp.366-371
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• 2012

In this paper, we propose an electric circuit using one common-arm of H-Bridge inverters to reduce the number of switching components in the multi-level inverter combined with H-Bridge inverters and transformers. And furthermore, we suggested a new multi-level PWM inverter using PWM level to reduce THD (Total Harmonic Distortion). We use a phase-shift switching method that has the same rate of usage at each transformer. Also, we test the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of the control signal for the proposed multi-level PWM inverter.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.6
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• pp.1035-1042
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• 2017

In this paper, we implement a public address system using power line communication in order to operate, extend, and expand the complicated public address devices and cables easily. Power line communication based public address system implemented consists of a public address control board and public address speaker boards which are suitable to digital streaming modulation. It can be noticed that we met satisfied results from performance measurement such as maximum audio output, audio channel response time, audio output SNR, and audio output THD+N.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.172-178
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes.