• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.106-113
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• 2000

This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.603-603
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• 2012

최근에 전면 emitter의 doping profile이 다른 selective emitter solar cell은 실제 제작시단파장 영역에서 많은 gain을 얻을 수 없어 LBC 구조의 태양전지에 관한 연구가 많이 진행되고 있다. 본 연구는 TCAD simulation을 이용하여 후면에 형성되는 locally doped BSF(p++) region의 doping profile의 변화에 따른 태양전지 특성에 관한 연구이다. Al으로 형성되는 local back contact의 doping depth 및 surface concentration에 따른 전기적, 광학적 분석을 통해 주도적인 인자를 분석하고 최적화하였다. 특히 doping depth에 따른 변화보다는 surface concentration의 변화에 따른 특성변화가 주도적으로 나타났다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.321-324
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• 2001

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased packing density. This paper has compared Micro-Tec with ISE-TCAD. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths 180nm. We have presented MOSF ET's characteristics such as I-V characteristic, electric field. and compared with Micro-Tec and ISE-TCAD.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.108-116
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• 1996

A semiconductor process imulator operated in windows$^{TM}$ environment has been developed. two-dimensional process simulation in personal computer has been enabled due to the improvement of CPU speed and the efficient use of memory. The process simulator in this paper is capable of calculating diffusion, oxidation, ion implantation, etching and deposition in two-dimensional manner. In addition, graphic-user-friendly editor, parser, and multi-dimensional graphical routine is also available in the devloped simulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.573-579
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high -integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. As devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impact ionization, electric field and I-V curve with those of lightly doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.311-316
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. At devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and also newEPI MOSFET for improved structure to weak point of LDD structure by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impart ionization, electric field and I-V curve with those of lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.

• Journal of the Semiconductor & Display Technology
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• v.4 no.1 s.10
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• pp.23-27
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• 2005

This paper presents a simulation methodology for the poly-silicon oriented TCAD(technology-CAD) system. A computer simulation environment for the poly-silicon processing has been set up with the proper adoption of the two-stream model for ion-doping, diffusion, and defects inside of grain and on the grain boundary. After the simulator calibration, simulation results for the poly-silicon diffusion hat shown a good agreement with the SIMS data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.