• 전자공학회논문지A
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• 제33A권2호
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• pp.163-172
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• 1996

In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

• 전자공학회논문지C
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• 제34C권10호
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• 한국통신학회논문지
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• 제15권10호
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• pp.819-828
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• 1990

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 전자공학회논문지B
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• 제33B권2호
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• pp.103-110
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• 1996

In this paper, we propose a unified systolic array for the computation of the 2D discrete cosine transform/discrete sine transform/discrete hartley transform (DCT/DST/DHT). The unified systeolic array for the 2D DCT/DST/DHT is a generalization of the unified systolic array for the 1D DCT/DST/DHT. In order to calculate the 2D transform, we compute 1D transforms along the row, transpose them, and obtain 1D transforms along the column. When we compare the proposed systolic array with the conventional method, our architecture exhibits a lot of advantages in terms of latency, throughput, and the number of PE's. The simulation results using very high speed integrated circuit hardware description language (VHDL), international standard language for hardware description, show the functional validity of the proposed architecture.

• 대한전자공학회논문지
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• 제26권8호
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• pp.1178-1186
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• 1989

In this paper, a systolic array for polyadic-nonserial DP problems is designed, the performance is analyzed and the efficient operating method is proposed. The algorithm is transformed to remove the broadcasting and global communication paths in the data dependence step by step. The transformed algorithm is mapping to the systolic array using the method proposed by D. I. Moldovan. The designed array is homogenous, had the processing elements of (n+1)/2 and 2n computation time ( n is the size of problem). In case of being many problems to process, the efficiency of array can be upward by inputing the problems successively. The interval between the initiations of two successive proboem instances is [n/2]+1 and the speed-up is about 4. The processor utilizations of each case are calculated.

• 전자공학회논문지B
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• 제30B권2호
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• 한국정보처리학회논문지
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• 제4권5호
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• pp.1380-1390
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• 1997

본 논문에서는 정규 순환방정식으로 표현된 n차원의 문제로부터 1차원이나 2 차원의 최적 평면 시스톨릭 어레이를 체계적으로 유도하는 방법과 이를 구현한 시스톨릭 어레이 설계시스텀을 제시한다. 구현된 시스템은 주어진 정규 순환방정식을 구문분석하여 문제공간, 자료종속 벡터와 초기값의 위치를 구한다. 이들 정보로부터 공간.시간 변환을 하여 자동으로 시스톨릭 어레이를 유도한다. 이스시템은 유도된 시스톨릭 어레이를 유도한다. 이 시스템은 유도된 시스톨릭 어레이의 병렬수행이 올바르게 이루어지는 지를 시각적으로 검증할 수 있게 해 준다.

• International Journal of Contents
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• 제9권1호
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.