• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.207-213
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• 1997

A field effect transistor(FET) type dissolved carbon dioxide($pCO_{2}$) sensor with a double layer structure of hydrogel membrane and $CO_{2}$ gas permeable membrane was fabricated by utilizing a $H^{+}$ ion selective field effect transistor(pH-ISFET) with Ag/AgCl reference electrode as a base chip. Formation of hydrogel membrane with photo-crosslinkable PVA-SbQ or PVP-PVAc/photosensitizer system was not suitable with the photolithographic process. Furthermore, hydrogel membrane on pH-ISFET base chip could be fabricated by photolithographic method with the aid of N,N,N',N'-tetramethyl othylenediarnine(TED) as $O_{2}$ quencher without using polyester film as a $O_{2}$ blanket during UV irradiation process. Photosensitive urethane acrylate type oligomer was used as gas permeable membrane on top of hydrogel layer. The FET type $pCO_{2}$ sensor fabricated by photolithographic method showed good linearity (linear calibration curve) in the range of $10^{-3}{\sim}10^{0}\;mol/{\ell}$ of dissolved $CO_{2}$ in aqueous solution with high sensitivity.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.5
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• pp.523-532
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• 2008

In this paper, we proposed a U-shaped RFID tag antenna with isotropic radiation characteristic for the stable operation of RFID system. The proposed antenna is composed of a U-shaped half wavelength dipole and a rectangular-shaped feed. In order to have good impedance matching with a tag chip, the commercial tag chip is attached to the lower center of the feed. A gain deviation characteristic of the U-shaped tag antenna can be further improved by inserting a rectangular slit in the lower center of the U-shaped antenna body. On the condition of VSWR<2, the tag antennas of two structures satisfy the Korea UHF RFID bandwidth and showed the gain deviation of less than 1.63 dB and 0.74 dB for without slit and with slit, respectively. On the condition of VSWR<5.8, the U-shaped tag antenna showed the gain deviation of less than 3.8 dB and 1.2 dB for without slit and with slit, respectively.

• Korean Journal of Agricultural Science
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• v.37 no.2
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• pp.191-197
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• 2010

The objective of this research was to determine the influence of the physical and chemical properties of root substrates used during the production of 'Maehyang' strawberry propaguleson the growth of the mother plants and the rate of daughter plant formation. Plants were cultured in plastic bags containing six different formulations of root substrates composed of: a) 50% coir dust and 50% perlite (5:5 by volume, A), b) 60% coir dust and 40% perlite (6:4, B), c) 70% coir dust and 30% perlite (7:3, C), d) 70% coir dust and 30% coconut chip (7:3 D), e) 60% coir dust and 40% coconut chip (60:40, E), or f) 50% sphagnum peat and 50% vermiculite (50:50, F). All media formulations contained a moderate level of base fertilizers. Physical and chemical properties of each formulation were determined before plant establishment and after 120 days of stock plant culture and runner production. Total porosity (TP) and container capacity (CC) of all substrate formulations were higher than 85% and 55%, respectively, allowing a suitable range of air and water holding characteristics. Formulation F provided the highest TP and CC values among the all substrate modifications evaluated. Substrate formulations A, B, C and F had higher electrical conductivity (EC) and $NO_3{^-}$-N concentrations than formulations D and E, when determined before and after plant culture. Formulations A, B, C, and F, having higher EC readings, also performed better as root substrates thanthe formulations D and E in increasing fresh and dry weights of the runners as well as the production of daughter plants per plant. The 'Maehyang' strawberry plants grown in the formulation F had the highest tissue N content, followed by those grown in substrate B, A, C, or D for 120 days after transplanting. Formulation F also facilitated accumulation of higher tissue phosphorus (P) and copper (Cu) contents compared to other treatments. Results of this experiment suggest that the chemical properties, rather than physical properties, of root substrates had a major influence on the growth of mother plants and the occurrence of healthy daughter plants during the bag-culture phase of propagation.

• Journal of Intelligence and Information Systems
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• v.28 no.3
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• pp.209-235
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• 2022

Starting from 2010, blockchain technology, along with the development of artificial intelligence, has been in the spotlight as the latest technology to lead the 4th industrial revolution. Furthermore, previous research regarding blockchain's technological applications has been ongoing ever since. However, few studies have been examined the standards for classifying the blockchain economic ecosystem from a capital market perspective. Our study is classified into a collection of interviews of software developers, entrepreneurs, market participants and experts who use blockchain technology to utilize the blockchain economic ecosystem from a capital market perspective for investing in stocks, and case study methodologies of blockchain economic ecosystem according to application fields of blockchain technology. Additionally, as a way that can be used in connection with equity investment in the capital market, the blockchain economic ecosystem classification methodology was established to form an investment universe consisting of global blue-chip stocks. It also helped construct an intelligent portfolio through quantitative and qualitative analysis that are based on quant and artificial intelligence strategies and evaluate its performances. Lastly, it presented a successful investment strategy according to the growth of blockchain economic ecosystem. This study not only classifies and analyzes blockchain standardization as a blockchain economic ecosystem from a capital market, rather than a technical, point of view, but also constructs a portfolio that targets global blue-chip stocks while also developing strategies to achieve superior performances. This study provides insights that are fused with global equity investment from the perspectives of investment theory and the economy. Therefore, it has practical implications that can contribute to the development of capital markets.

• Korean Journal of Optics and Photonics
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• v.6 no.3
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• pp.188-200
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• 1995

A design of unit magnification 2-mirror system with high resolution is presented. It is for soft X-ray(wavelength of 13 nm) projection imaging and suitable for preparation of high density semiconductor chip. In general, a holosymmetric system with unit magnification has the advantage that both coma and distortion are completely eliminated. In our holosymmetric 2-mirror system, spherical aberration is addtionally removed by using two identical paraboloidal mirror surfaces and field curvature aberration is also corrected by balancing Petzval sum and astigmatism which depends on the distance between two mirrors, so that the system is a aplanatic flat-field paraboloidal 2-mirror holosymmetric system. This 2-mirror system is small in size, and has a simple configuration with rotational symmetry about optical axis, and has also small central obscuration. Residual finite aberrations, spot diagrams, and diffraction-based MTF's are analyzed for the check of performances as soft X-ray lithography projection system. As a result, the image sizes for the resolutions of$0.25\mum$and $0.18\mum$are 4.0 mm, 2.5 mm respectively, and depths of focus for those are $2.5\mum$, $2.4\mum$respectively. This system should be useful in the fabrication of 256 Mega DRAM or 1 Giga DRAM. DRAM.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.247-252
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• 2013

In this paper, a microwave tag system of a frequency-scanning type is proposed with multi-resonators using defected ground structures. While a conventional chip-based RFID stores time-sequential codes, the proposed type achieves pure passive tags by using multi-resonant bits over a frequency range. Moreover, the resonators of the spiral defected ground structures implemented on the back side of transmission lines have advantages of the excellent bandstop characteristics as well as the bit-error avoidance by the re-radiation on normal resonators. The proposed microwave tag is designed with UWB antennas at 3~7 GHz. From the experimental results in an anechoic chamber, it has been verified of the excellent recognitions for various 5-bits identification codes.