• Title/Summary/Keyword: System-on-chip

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Analyses of Shear and Frictional Characteristics in Drilling Process (드릴링 공정의 전단 및 마찰 특성 해석)

  • Kim, Sun-Il;Choi, Won-Sik;Son, Jae-Hwan;Jang, Eun-Suk;Lee, Young-Moon
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.11 no.6
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    • pp.22-27
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    • 2012
  • Drilling process is usually the most efficient and economical method of making a hole in a solid body. However, there have been no analytical method to assess drilling process based on the shear and frictional characteristics. In this paper, procedures for analyzing shear and frictional processes of drilling have been established by adopting an equivalent turning system to drilling. A series of drilling experiments were carried out with varying feed, velocity and drill shape factors. Using the results of the experiments, the cutting characteristics including shear in the primary shear zone and friction in the chip-tool contact region of drilling process have been analyzed. The specific cutting energy tends to decrease exponentially with increase of feed rate. In drilling process 35-40% of the total energy is consumed in the friction process. This is greater than that of turning process in cutting of the same work material.

Computationally-Efficient Algorithms for Multiuser Detection in Short Code Wideband CDMA TDD Systems

  • De, Parthapratim
    • Journal of Communications and Networks
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    • v.18 no.1
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    • pp.27-39
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    • 2016
  • This paper derives and analyzes a novel block fast Fourier transform (FFT) based joint detection algorithm. The paper compares the performance and complexity of the novel block-FFT based joint detector to that of the Cholesky based joint detector and single user detection algorithms. The novel algorithm can operate at chip rate sampling, as well as higher sampling rates. For the performance/complexity analysis, the time division duplex (TDD) mode of a wideband code division multiplex access (WCDMA) is considered. The results indicate that the performance of the fast FFT based joint detector is comparable to that of the Cholesky based joint detector, and much superior to that of single user detection algorithms. On the other hand, the complexity of the fast FFT based joint detector is significantly lower than that of the Cholesky based joint detector and less than that of the single user detection algorithms. For the Cholesky based joint detector, the approximate Cholesky decomposition is applied. Moreover, the novel method can also be applied to any generic multiple-input-multiple-output (MIMO) system.

Development of PLC Device for White Goods based on Web Technology (Web 기반의 백색 가전기기의 전력선 통신 장치 개발)

  • Myoung, Kwan-Joo;Kim, Dong-Sung;Cho, Sung-Guk;Kwon, Wook-Hyun;Kim, Yo-Hee
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2646-2648
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    • 2001
  • In this paper, the development of Power Line Communication(PLC) device for white goods is presented. The commercial PLC chip-set is used for the modem device of white goods. As a PLC device for white goods, an ARM720 u-controller and a windows CE 3.0 are adopted. UPnP (Universal Plug and Play) that is applied for home network middle ware in implemented system. In addition, application programming and emulator for home appliance are implemented using UPnP standard ver 1.0.

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Through Silicon Stack (TSS) Assembly for Wide IO Memory to Logic Devices Integration and Its Signal Integrity Challenges

  • Shin, Jaemin;Kim, Dong Wook
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.2
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    • pp.51-57
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    • 2013
  • The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

A Study on DC-DC Power Supply for Maglev (자기부상열차용 DC-DC 전원장치에 관한 연구)

  • Chung, Choon-Byung;Cho, Ju-Hyun;Jho, Jung-Min;Jeon, Kee-Young;Lee, Sang-Chip;Oh, Bong-Hwan;Lee, Hoon-Gu;Han, Kyung-Hee
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2004.05a
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    • pp.347-352
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    • 2004
  • The author present a modified multi-loop algorithm including feedforward for controlling a 55kW step down chopper in the power supply of Maglev. The control law for the duty cycle consists of three terms. The first is the feedforward term which compensates for variations in the input voltage. The second term consists of the difference between the slowly moving inductor current and output current. The third term consists of proportional and integral terms involving the perturbation in the output voltage. This perturvation is derived by subtracting the desired output voltage from the actual output voltage. The proportional and integral action stabilizes the system and minimizes output voltage error. In order to verify the validity of the proposed multi-loop controller, simulation study was tried using Matlab simulink.

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Microcantilever-based biosensor using the surface micromachining technique (표면 미세 가공기술을 이용한 마이크로 캔틸레버의 제작과 바이오션서로의 응용)

  • Yoo, Kyung-Ah;Joung, Seung-Ryong;Kang, Chi-Jung;Kim, Yong-Sang
    • Proceedings of the KIEE Conference
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    • 2005.07c
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    • pp.2407-2409
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    • 2005
  • 본 논문에서는 다양한 생물분자 감지를 위한 센서로 마이크로캔틸레버를 제안하였고 이것을 이용해 여러 생물 분자들을 광학적, 전기적으로 분석하였다. 마이로캔틸레버는 표면 미세 가공 기술로 제작되었고, 이러한 제작 방식은 공정이 간단하고 비용이 적게 들며 센서 array가 가능하다는 장점을 갖는다. 생물분자를 포함하는 용액을 주입하기 위하여 PDMS와 fused silica glass를 이용해 fluid cell system을 제작하였다. 마이크로캔틸레버 상단의 gold가 코팅된 부분에서 생물분자의 자기조립 (self assembly)현상이 일어나고 이는 마이크로캔틸레버 상, 하단의 표면 스트레스 차이를 야기 시킨다. 이로 인해 마이크로캔틸레버 자체의 휘어짐 현상이 일어나게 되고 이러한 휘어진 정도를 측정함으로써 마이크로캔틸레버의 생물분자 감지능을 확인할 수 있었다. Cystamine dihydrochloride와 glutaraldehyde 분자를 분석하였고 각기 다른 농도의 cystamine dihydrochloride 용액에서도 실험함으로써 농도별 감지능 또한 확인하였다. 이러한 생물분자 감지를 위한 마이크로캔틸레버의 센서로써의 성능은 u-TAS 와 lab-on-a-chip에서 유용히 이용될 수 있으리라 확신한다.

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A study on the adjusting output energy of the CO2 laser controlled directly in AC power line (상용전원을 제어하는 CO2레이저의 출력 조절에 관한 연구)

  • Jeong, Jong-Jin;Lee, Im-Geun;Choi, Jin-Young;Park, Sung-Jin;Song, Gun-Ju;Kim, Hee-Je
    • Proceedings of the KIEE Conference
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    • 2005.07c
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    • pp.2138-2139
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    • 2005
  • We demonstrate a simple CO2 laser by controlling firing angle of a TRIAC switch in ac power line. The power supply for our laser system switches the voltage of the AC power line (60Hz) directly. The power supply does not need elements such as a rectifier bridge, energy-storage capacitors, or a current-limiting resistor in the discharge circuit. In order to control the laser output power, the pulse repetition rate is adjusted up to 60Hz and the firing angle of TRIAC gate is varied from 45 to 135. A ZCS(Zero Crossing Switch) circuit and a PIC one-chip microprocessor are used to control the gate signal of the TRIAC precisely. The maximum laser output of 40W is obtained at a total pressure of 18Torr, a pulse repetition rate of 60Hz, and a TRAIC gate firing angle of 90.

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A Design of Direct conversion method 2.45GHz Low-IF Mixer Using CMOS 0.18um Process (CMOS 0.18um 공정을 이용한 2.45GHz Low-IF 직접 변환 방식 혼합기 설계)

  • Choi, Jin-Kyu;Kim, Hyeong-Seok
    • 한국정보통신설비학회:학술대회논문집
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    • 2008.08a
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    • pp.414-417
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    • 2008
  • This paper presents the design and analysis of 2.45GHz Low-IF Mixer using CMOS 0.18um. The Mixer is implemented by using the Gilbert-type configuration, current bleeding technique, and the resonating technique for the tail capacitance. And the design of this Double Balance Mixer is based on its lineaity since it is important in the interference cancellation system. The low flicker noise mixer is implemented by incorporating a double balanced Gilber-type configuration, the RF leakage-less current bleeding technique, and Cp resonating technique. The proposed mixer has a simulated conversion gain of 16dB a simulated IIP3 of -3.3dBm and P1dB is -19dBm. A simulated noise figure of 6.9dB at l0MHz and a flicker corner frequency of 510kHz while consuming only 10.65mW od DC power. The layout of Mixer for one-chip design in a 0.18-um TSMC process has 0.474mm$\times$0.39 mm size.

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Development of the Air Stick Feeder for Inserting the Relay (릴레이 삽입을 위한 에어 스틱 피더의 개발)

  • Kim, Young-Min;Kim, Chi-Su
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.2
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    • pp.1398-1402
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    • 2015
  • In surface mount technology, the use of technology implemented using a Chip Mounter relay that is inserted into the junction box, etc. car is increasing. On the other hand, there is a need for technology to reduce the weight of the heavy component of the relay attached to different Stick Tube generally chips. Therefore, rather than existing technology, this study improved the algorithm of the system to provide a mechanical structure using Air to supply greater stability using this the component feeder utilizing the Stick Tube proposed technology. When the equipment installed in the Air Stick Feeder was used, the effectiveness, such as increased production and reduced disposal expense, was improved.

Fault-Tolerant Design of Array Systems Using Multichip Modules (다중칩을 이용한 어레이시스템의 결함허용 설계)

  • Kim, Sung-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.12
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    • pp.3662-3674
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    • 1999
  • This paper addresses some design issues for establishing the optimal number of spare units in array systems manufactured using fault-tolerant multichip modules(MCM's) for massively parallel computing(MPC). We propose a new quantitative approach to an optimal cost-effective MCM system design under yield and reliability constraints. In the proposed approach, we analyze the effect of residual redundancy on operational reliability of fault-tolerant MCM's. In particular, the issues of imperfect support circuitry, chip assembly yield and array topology are investigated. Extensive parametric results for the analysis are provided to show that our scheme can be applied to design ways using MCM's for MPC applications more efficiently, subject to yield and reliability constraints.

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