• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.188-198
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• 2010

Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Institute of Convergence Signal Processing
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• v.23 no.2
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• pp.91-96
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• 2022

At the current camera-based technology level, sensor-based basic life pattern recognition technology has to suffer inconvenience to obtain accurate data, and commercial band products are difficult to collect accurate data, and cannot take into account the motive, cause, and psychological effect of behavior. the current situation. In this paper, radar technology for life pattern recognition is a technology that measures the distance, speed, and angle with an object by transmitting a waveform designed to detect nearby people or objects in daily life and processing the reflected received signal. It was designed to supplement issues such as privacy protection in the existing image-based service by applying it. For the implementation of the proposed system, based on TI IWR1642 chip, RF chipset control for 60GHz band millimeter wave FMCW transmission/reception, module development for distance/speed/angle detection, and technology including signal processing software were implemented. It is expected that analysis of individual life patterns will be possible by calculating self-management and behavior sequences by extracting personalized life patterns through quantitative analysis of life patterns as meta-analysis of living information in security and safe guards application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Smart Structures and Systems
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• v.12 no.1
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• pp.1-22
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• 2013

Magnetic nanoparticle based bioseparation in microfluidics is a multiphysics phenomenon that involves interplay of various parameters. The ability to understand the dynamics of these parameters is a prerequisite for designing and developing more efficient magnetic cell/bio-particle separation systems. Therefore, in this work proof-of-concept experiments are combined with advanced numerical simulation to design and optimize the capturing process of magnetic nanoparticles responsible for efficient microfluidic bioseparation. A low cost generic microfluidic platform was developed using a novel micromolding method that can be done without a clean room techniques and at much lower cost and time. Parametric analysis using both experiments and theoretical predictions were performed. It was found that flow rate and magnetic field strength greatly influence the transport of magnetic nanoparticles in the microchannel and control the capturing efficiency. The results from mathematical model agree very well with experiments. The model further demonstrated that a 12% increase in capturing efficiency can be achieved by introducing of iron-grooved bar in the microfluidic setup that resulted in increase in magnetic field gradient. The numerical simulations were helpful in testing and optimizing key design parameters. Overall, this work demonstrated that a simple low cost experimental proof-of-concept setup can be synchronized with advanced numerical simulation not only to enhance the functional performance of magneto-fluidic capturing systems but also to efficiently design and develop microfluidic bioseparation systems for biomedical applications.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.9-14
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• 2012

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.1
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• pp.91-98
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• 2010

The increasing of power and processing speed and miniaturization of central processor unit (CPU) used in electronics equipment requires better performing thermal management systems. A typical thermal management package consists of thermal interfaces, heat dissipaters, and external cooling systems. There have been a number of experimental techniques and procedures for estimating thermal conductivity of thin, compressible thermal interface material (TIM). The TIM performance is affected by many factors and thus TIM should be evaluated under specified application conditions. In compact packaging of electronic equipment the chip is interfaced with a thin heat spreader. As the package is made thinner, the coupling between heat flow through TIM and that in the heat spreader becomes stronger. Thus, a TIM characterization system for considering the heat spreader effect is proposed and demonstrated in detail in this paper. The TIM test apparatus developed based on ASTM D-5470 standard for thermal interface resistance measurement of high performance TIM, including the precise measurement of changes in in-situ materials thickness. Thermal impedances are measured and compared for different directions of heat dissipation. The measurement of the TIM under the practical conditions can thus be used as the thermal criteria for the TIM selection.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.178-178
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• 2009

전자제품의 고속화, 고집적화, 고성능이 요구되어짐에 따라 IC's 성능 향상을 통해 패키징 기술의 소형화를 필요로 하고 있어 소재나 칩 부품을 이용해 커패시터나 저항을 구현하여 내장시키는 임베디드 패시브 기술에 대한 연구가 많이 진행되어 지고 있다. 본 연구에서는 3D 패키징이 가능한 flexible 소재에 능, 수동 소자를 내장하기 위한 다층 flexible 기판 공정 기술에 대한 연구를 수행하였다. 기판제작을 위해 flexible 소재에 미세 형성이 가능한 폴리머 필름을 접착하였고 flexible 위에 후막 저항체 패턴을 퍼|이스트를 이용하여 형성하였다. 또한, 능동소자 내장을 위해 test chip을 제작하여 플립칩 본더를 이용해 flexible 기판에 접합한 후에 bonding film을 이용한 build up 공정을 통해 via를 형성하고 무전해 도금 공정을 거쳐 전기적인 연결을 하였다. 위의 공정을 통해 앓고 가벼울 뿐만 아니라 자유롭게 구부러지는 특성을 갖고 있는 능, 수동 소자 내장형 flexible 기판의 변형에 따른 전기적 특성을 평가하였다.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.6-12
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• 2006

A popular method used by primary protection for power transformer is current ratio differential relaying (RDR) with 2nd harmonic restraints. In modern power transformer due to the use of low-loss amorphous material, the 2nd harmonic component during inrush is significantly reduced. The higher the capacitance of the high voltage status and underground distribution, the more the differential current includes the 2nd harmonic component during internal fault. Thus the conventional method may not operate properly. This paper proposes an advanced relaying algorithm and the prototype IED hardware design and it's real-time experimental results. To evaluate performance of the proposed algorithm, the study is well constructed power system model including power transformer utilizing the EMTP software and the testing is made through simulation of various cases. The proposed relaying that is well constructed using DSP chip and microprocessor etc. has been developed and the prototype IED has been verified through on-line testing. The results show that an advanced relaying based prototype IED never mis-operated and correctly identified all the faults and that inrushes that are applied.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.156-161
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• 2004

The MMIC cascode VCO is designed, fabricated, and measured for Ku-band Low Noise Blcok(LNB) system using InGaP/GaAs HBT technology. The phase noise of -116.4 dBc/Hz at 1 MHz offset with output power of 1.3 dBm is obtained at 11.526 GHz by applying 3 V and 11 mA, which is comparatively better characteristics than compared with the different configuration VCOs fabricated with other technologies. The simulated results of oscillation frequency and second harmonic suppression agree with the measured results. The phase noise is improved due to the use of the smallest value of inductor in frequency determining network and the InGaP ledge function of the technology. The chip size of $830\time781\;{\mu}m^2$ is also achieved.