• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.5
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• pp.2325-2331
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• 2012

Planar square-spiral antenna using a strip conductor is proposed and analyzed for RFID system in UHF band operating from 860MHz to 960MHz. By varying the length of common line, detached distance, strip line-space, strip line-width and the number of spiral turn, the optimized antenna are designed and fabricated in compact size without a matching-stub between the input port of the proposed antenna and RFID tag chip. From the optimized results, the frequency bandwidth in VSWR<2 has covered 100MHz in the RFID UHF band. The antenna gain has obtained 3.5dBi at the center frequency of 910MHz and the desired beam pattern has shown directional pattern on elevation and azimuth angle. Therefore, the proposed antenna is suitable for practical RFID applications requiring various tag chips with the specific input impedance.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• The Korean Journal of Physiology and Pharmacology
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• v.10 no.5
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• pp.263-271
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• 2006

Since astrocytes were shown to play a central role in maintaining neuronal viability both under normal conditions and during stress such as ischemia, studies of the astrocytic response to stress are essential to understand many types of brain pathology. The micro array system permitted screening of large numbers of genes in biological or pathological processes. Therefore, the gene expression patterns in the in vitro model of astrocytes following exposure to oxygen-glucose deprivation (OGD) were evaluated by using the micro array analysis. Primary astrocytic cultures were prepared from postnatal Swiss Webster mice. The cells were exposed to OGD for 4 hrs at $37^{\circ}C$ prior to cell harvesting. From the cultured cells, we isolated mRNA, synthesized cDNA, converted to biotinylated cRNA and then reacted with GeneChips. The data were normalized and analyzed using dChip and GenMAPP tools. After 4 hrs exposure to OGD, 4 genes were increased more than 2 folds and 51 genes were decreased more than 2 folds compared with the control condition. The data suggest that the OGD has general suppressive effect on the gene expression with the exception of some genes which are related with ischemic cell death directly or indirectly. These genes are mainly involved in apoptotic and protein translation pathways and gap junction component. These results suggest that microarray analysis of gene expression may be useful for screening novel molecular mediators of astrocyte response to ischemic injury and making profound understanding of the cellular mechanisms as a whole. Such a screening technique should provide insights into the molecular basis of brain disorders and help to identify potential targets for therapy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of Korean Society for Quality Management
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• v.31 no.4
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• pp.81-94
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• 2003

Six sigma is a management innovation strategy which improves all managerial processes in an integrated manner, Six sigma can be applied to every aspect of managerial functions such as marketing, engineering, purchasing, accounting, and so on. Six sigma is trying to solve quality problems from the customer's viewpoint in the scientific manner, thus maximizing profits through the elimination of quality costs. This paper is presented to verify empirically the successful factors of implementing six sigma through the survey of black­belts of Korean firms. The blue­chip companies in Korea and across the world have already adopted Six Sigma, and it is becoming an integral part of the corporate culture of these companies. In conclusion, the most important factors to the success of six sigma are found to be the leadership of top management, and the compensation/ incentive system. The analysis also shows that the important factors are different in terms of both the process type and implementing stage.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.7
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• pp.56-62
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• 2019

The high-precision laser scriber carries out scribing alumina ceramic substrates for manufacturing ultra-small chip resistors. The ceramic substrates are loaded, aligned, scribed, transferred, and unloaded. The entire process is fully automated, thereby minimizing the scribing cycle time of the ceramic substrates and improving the throughput. The scriber consists of the laser optical system, pick-up module of ceramic substrates, pre-alignment module, TH axis drive work table, automation module for substrate loading / unloading, and high-speed scribing control S/W. The loader / unloader unit, which has the greatest influence on the scribing cycle time of the substrates, carries the substrates to the work table that carries out the cutting line work by driving the X and Y axes as well as by adsorbing the ceramic substrates. The loader / unloader unit consists of the magazine up / down part, X-axis drive part for conveying the substrates to the left and right direction, and the vision part for detecting the edge of the substrate for the primary pre-alignment of the substrates. In this paper, the laser scribing machining simulation is performed by applying the instrument mechanism of each component module. Through this study, the scribing machining process is first verified by analyzing the process operation and work area of each module in advance. In addition, the scribing machining process is optimized by comparing and analyzing the scribing cycle time of one ceramic substrate according to the alignment stage module speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.277-280
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• 2016

Currently, systems for finding missing children are composed of using communication between a QR code and RFID chip, as the use of a smartphone. However, the current systems for finding missing children have limitations in that children can only be found if there are people in the surrounding area; there is an economic burden on parents required to purchase a smartphone for their children; along with difficulties in finding the missing children without the assistance of those in the surrounding area in critical situations such as a kidnapping, due to the limited duration of the battery life. In order to solve such problems, approaches need to be made from two perspectives: having someone in the surrounding area; and absence of anyone in the surrounding area. This thesis is centered on the development of a IoT (Internet of Things) system for finding missing children that combines two methods, namely, the method of finding missing children without a guardian in the surrounding area -within the limited space in which AP is installed by using a beacon and open source hardware being highlighted as the IoT technology - and the method of finding missing children with the smartphone application in which each individual becomes the Access Point (AP). The Main purpose is to provide accurate information of missing children's location for the 2situations and it is found that the accuracy of smartphones APP is 97.7% and security device AP is 91.1%.