• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.15-21
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• 2011

In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.

• Proceedings of KOSOMES biannual meeting
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• 2005.11a
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• pp.197-202
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• 2005

Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection using subpixel edge detection method in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• Journal of the Korea Computer Industry Society
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• v.2 no.8
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• pp.1055-1062
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• 2001

Study, it is the purpose to develope a cheap and compact pulsed $CO_2$ laser with pulse repetition rate range of 1 KHz. We used a IGBT switched power supply as a power supply, which is cheap and simple comparing to others. PIC one-chip microprocessor was used for precise control of a laser power supply on the control part. And the laser cavity was fabricated as an axial and water cooled type. The laser performance characteristics as various parameters, such as pulse repetition rate, gas pressure, and gas mixture rate have been investigated. The experiment was done under the condition of total pressure of $CO_2$： $N_2$：He ＝ 1：3：10, 1：1.5：5, 1：9：15 from 6 Torr to 15 Torr and pulse repetition rate from 100 Hz to 900 Hz. As a result, the maximum average outpu was about 20.5 W at the total pressure of 15 Torr, the gas mixture $CO_2$：$N_2$：He ＝ 1：9：15 and the pulse repetition rate of 700 Hz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.131-137
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• 2009

Binary offset carrier (BOC) signal synchronization is one of the most important steps to recover the transmitted information in global navigation satellite systems (GNSS) including Galileo and global positioning system (GPS). Generally, BOC signal synchronization is based on the correlation between the received and locally generated BOC signals. Thus, the multiple side-peaks in BOC autocorrelation are one of the main error sources in synchronizing BOC signals. Recently, a novel correlation function with reduced side-peaks was proposed for BOC signal synchronization by Julien [8]; however, Julien's correlation function not only still has the side-peaks, but also is only applicable to sine phased BOC(n, n), where n is the ratio of the pseudo random noise (PRN) code rate to 1.023 MHz. In this paper, we propose a new correlation function for BOC signal synchronization, which does not have any side-peaks and is applicable to general types of BOC signals, sine/cosine phased BOC(kn, n), where k is the ratio of a PRN chip duration to the period of a square wave sub-carrier used in BOC modulation. In addition, an efficient correlator structure is presented for generating the proposed correlation function.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• The KIPS Transactions:PartB
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• v.9B no.4
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• pp.429-436
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• 2002

In order to apply the artificial neural network to the practical application, it is needed to implement it with the hardware system. It is most promising to make it with the hybrid VLSI among various possible technologies. When we Implement a trained network into the hybrid neuro-chips, it is to be performed the process of the quantization on its neuron outputs and its weights. Unfortunately this process cause the network's outputs to be distorted from the original trained outputs. In this paper we analysed in detail the statistical characteristics of the distortion. The analysis implies that the network is to be trained using the normalized input patterns and finally into the solution with the small weights to reduce the distortion of the network's outputs. We performed the experiment on an application in the time series prediction area to investigate the effectiveness of the results of the analysis. The experiment showed that the network by our method has more smaller distortion compared with the regular network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.20-25
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• 2010

An integrated Mach-Zehnder interferometric sensor operating at 632.8 nm was designed and fabricated by the technology of planar rib waveguides. Rib waveguide based on silica system ($SiO_2-SiO_xN_y-SiO_2$) was geometrically designed to have single mode operation and high sensitivity. It was structured by semiconductor fabrication processes such as thin film deposition, photolithography, and RIE (Reactive Ion Etching). With the power observation, propagation loss measurement by cut-back method showed about 4.82 dB/cm for rib waveguides. Additionally the chromium mask process for an etch stop was employed to solve the core damaging problem in patterning the sensing zone on the chip. Refractive index measurement of water/ethanol mixture with this device finally showed a sensitivity of about $\pi$/($4.04{\times}10^{-3}$).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.4
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• pp.55-62
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• 2004

In this paper, we have developed a portable acceleration measurement system to measure acceleration signals during walking and a gait analysis algorithm which can evaluate gait regularity and symmetry and estimate gait parameters automatically. Portable acceleration measurement system consists of a biaxial accelerometer, amplifiers, lowpass filter with cut-off frequency of 16Hz, one-chip microcontroller, EEPROM and RF(TX/RX) module. The algerian includes FFT analysis, filter processing and detection of main peaks. In order to develop the algorithm, eight hemiplegic patients for training set and the other eight hemiplegic patients for test set are participated in the experiment. Acceleration signals during 10m walking were measured at 60 samples/sec from a biaxial accelerometer mounted between L3 and L4 intervertebral area. The algorithm, detected foot contacts and classified right/left steps, and then calculated gait parameters based on these informations. Compared with video data and analysis by manual, algorithm showed good performance in detection of foot contacts and classification of right/left steps in test set perfectly. In the future, with improving the reliability and ability of the algerian so that calculate more gait Parameters accurately, this system and algerian could be used to evaluate improvement of walking ability in hemiplegic patients in clinical practice.