• Journal of Multimedia Information System
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• 제5권4호
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.74-80
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• 2002

SOC와 같은 VLSI 집적 회로는 기능적 이유 등으로 인해 다중 클락의 설계 기법을 필요로 한다. 테스트시 클락 오더링과 같은 문제의 효과적이지 못한 대응으로 인해 클락 도메인간의 전이에서 많은 오류들이 발생한다. 본 논문은 다중 클락 시스템에서의 새로운 자체 테스크 기법을 제시한다. 클락 스큐의 문제는 다중캡처의 동작으로 제거하며, 다른 클락 도메인간 혹은 같은 클락 도메인간의 테스트 모두를 동작속도에서 가능하게 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• 인포메이션 디스플레이
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• 제5권1호
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• pp.25-30
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• 2004

Poly-Si TFT(Thin Film Transistor) technology are reviewed and discussed. Poly-Si TFTs fabricated on glass using low-temperature process were studied extensively for the application to LCD (Liquid Crystal Display) as well as to OLED(Organic Light Emitting Diode) Display. Currently, one of the application targets of the poly-Si TFT is emphasized on the highly functional SOG(System on Glass). Improvement of device characteristics such as an enhancement of carrier mobility has been studied intensively by enlarging the grain size. Reduction of the voltage and shrinkage of the device size are the trend of AM FPD(Active Matrix Flat Panel Display) as well as of Si LSI, which will arise a peculiar issue of uniformity for the device performance. Some approaches such as nucleation control of the grain seed or lateral grain growth have been tried, so far.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.570-573
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• 2004

This paper present a distributed RC lines (URCs) oscillator with sinusoidal output. The frequency of oscillator can be controlled and adjustable by varying an one pole amplifier. The circuit incorporated an gain controller loop for amplitude stabilization with low distortion. The realization of simulation and experimental results are in reasonably good agreement with the theoretical , and very low harmonic distortion. In this circuit can be suitable for LSI process fabrication and the circuit application in electronic communications system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.137-140
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• 2002

In this paper, a new algorithm for two-dimensional (2-D) finite-difference time-domain (FDTD) method is presented. By this new method, the maximum time step size can be increased over the Courant-Friedrich-Levy (CFL) condition restraint. This new algorithm is adapted from an Alternating-Direction Implicit FDTD (ADI-FDTD) method. However, unlike the ADI-FDTD algorithm. the alternation is performed with respect to the blocks of fields rather than with respect to each respective coordinate direction. Moreover. this method can be efficiently simulated with parallel computation. and it is more efficient than the conventional FDTD method in terms of CPU time. Numerical formulations are shown and simulation results are presented to demonstrate the effectiveness and efficiency of our proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• 전기전자학회논문지
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• 제3권1호
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.1864-1872
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• 2014

Maloperation of protective relays is one of the major causes for cascading tripping in WANS. Another line trip followed by a previous line trip may occur due to overloading of the line, because of the load redistribution or unwanted trip of a backup relay due to change in the flow of fault current. Evaluation of each line is required by considering both of these effects. A new index named Line Security Index (LSI) is proposed in this paper which combines both Vulnerability Index (VI) and Protectability Index (PI) to completely evaluate the security of individual lines and their importance in the power grid. Computer simulations have been performed on the Korean power grid data to establish the feasibility of the proposed idea.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2002년도 하계학술대회 및 세미나
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• pp.21-23
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• 2002

In millimeter wave applications, it is often necessary to use transitions between waveguide and planar circuits. Finline structures can be used effectively to this purpose. In multilayered case, it is necessary to analyze the structure with numerical method such as spectral domain immittance method. The design procedure uses tile cutoff frequency for each taper width. The dispersion data in a single layer are compared with those in literature. The performance of the designed finline taper is verified with the FEM simulation using HFSS.