• The Transactions of The Korean Institute of Electrical Engineers
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• 제58권10호
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Proceedings of the KIEE Conference
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• 대한전기학회 2006년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.166-168
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• 2006

This paper presents a speed control of AC servo system using LabVIEW program and cRIO (Compact RIO)hardware which is a real-time controller made in National Instruments company. LabVIEW is a GUI programming language easy to implement control system and cRIO is a reconfigurable hardware platform which is very simple. Therefore Lab VIEW and cRIO will be excellent tools to design and implement control system.

• The Transactions of the Korean Institute of Electrical Engineers
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• 제45권4호
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• pp.474-483
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• 1996

In this paper, as a part of the method improving stability, the load-flow calculation in D.C. power system and the models for stability analysis are studied with A.C-D.C. interconnected power systems transmission performed. Moreover, the theory is established in relation to each control method of D.C. power systems. Then the stability of A.C-D.C.interconnected power systems is compared and considered by the way of dividing the operating control method of the rectifier inverter converter into ACR-AVR, APR-A.gamma.R, A.alpha.R-ACR. The dynamics characteristic of terminal voltage, frequency, active-reactive power and rotor angle of the generator with disturbances and load fluctuations is considered. In addition, the characteristic of direct voltage, direct current, power and control systems. From this the comparative analysis of the direct current control method, the possibility of the stability analysis of A.C.-D.C. interconnected power system is considered. (author). refs., figs., tabs.

• Journal of the Institute of Convergence Signal Processing
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• 제12권4호
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• pp.309-314
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• 2011

As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

• Journal of the Institute of Convergence Signal Processing
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• 제10권4호
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제19권8호
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Journal of the Institute of Convergence Signal Processing
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• 제11권2호
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.

• Journal of Korea Multimedia Society
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• 제19권2호
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• pp.122-127
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• 2016

This paper propose implementation method of SoC system for efficient depth image segmentation. SoC systems are combined platform in the form of the Software and Hardware IP. In order to perform effectively, the user to determine the operation of the configuration of each part. In this paper, we implemented a segmentation of depth images taken by the infrared sensor at APU of SoC system. The proposed method efficiently implements high performance and low power in SoC system. Proposed method that using software parts of SoC system is capable to use at several depth image processing systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.

• Journal of the Korean Ceramic Society
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• 제27권4호
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• pp.560-566
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• 1990

The early hydration characteristics according to the C3A polymorphism and the presence of gypsum, in order to establish the hydration mechanism of the system C3S-C3A, have been studied. The hydration rate of C3A was changed according to the its crystal structure and influenced the hydration of C3S. That is, the hydration rate of C3S was accelerated in case of orthorhombic-C3A, but that was slightly retarded in case of melt-C3A than that of cubic-C3A. In the system C3S-C3A-gypsum, the retardation phenomenon of the reaction of monosulfate formation was observed in case of both orthorhombic and melt-C3A.